1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) Marvell International Ltd. and its affiliates
4 */
5
6#ifndef _DDR3_TRAINING_IP_ENGINE_H_
7#define _DDR3_TRAINING_IP_ENGINE_H_
8
9#include "ddr3_training_ip_def.h"
10#include "ddr3_training_ip_flow.h"
11#include "ddr3_training_ip_pbs.h"
12
13#define EDGE_1				0
14#define EDGE_2				1
15#define ALL_PUP_TRAINING		0xe
16#define PUP_RESULT_EDGE_1_MASK		0xff
17#define PUP_RESULT_EDGE_2_MASK		(0xff << 8)
18#define PUP_LOCK_RESULT_BIT		25
19
20#define GET_TAP_RESULT(reg, edge)				 \
21	(((edge) == EDGE_1) ? ((reg) & PUP_RESULT_EDGE_1_MASK) : \
22	 (((reg) & PUP_RESULT_EDGE_2_MASK) >> 8));
23#define GET_LOCK_RESULT(reg)						\
24	(((reg) & (1<<PUP_LOCK_RESULT_BIT)) >> PUP_LOCK_RESULT_BIT)
25
26#define EDGE_FAILURE			128
27#define ALL_BITS_PER_PUP		128
28
29#define MIN_WINDOW_SIZE			6
30#define MAX_WINDOW_SIZE_RX		32
31#define MAX_WINDOW_SIZE_TX		64
32
33int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type,
34			      enum hws_search_dir search_dir,
35			      enum hws_dir direction,
36			      enum hws_edge_compare edge,
37			      u32 init_val1, u32 init_val2,
38			      u32 num_of_iterations, u32 start_pattern,
39			      u32 end_pattern);
40int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern);
41int ddr3_tip_load_all_pattern_to_mem(u32 dev_num);
42int ddr3_tip_read_training_result(u32 dev_num, u32 if_id,
43				  enum hws_access_type pup_access_type,
44				  u32 pup_num, u32 bit_num,
45				  enum hws_search_dir search,
46				  enum hws_dir direction,
47				  enum hws_training_result result_type,
48				  enum hws_training_load_op operation,
49				  u32 cs_num_type, u32 **load_res,
50				  int is_read_from_db, u8 cons_tap,
51				  int is_check_result_validity);
52int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type,
53			 u32 interface_num,
54			 enum hws_access_type pup_access_type,
55			 u32 pup_num, enum hws_training_result result_type,
56			 enum hws_control_element control_element,
57			 enum hws_search_dir search_dir, enum hws_dir direction,
58			 u32 interface_mask, u32 init_value, u32 num_iter,
59			 enum hws_pattern pattern,
60			 enum hws_edge_compare edge_comp,
61			 enum hws_ddr_cs cs_type, u32 cs_num,
62			 enum hws_training_ip_stat *train_status);
63int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
64				 u32 if_id,
65				 enum hws_access_type pup_access_type,
66				 u32 pup_num,
67				 enum hws_training_result result_type,
68				 enum hws_control_element control_element,
69				 enum hws_search_dir search_dir,
70				 enum hws_dir direction,
71				 u32 interface_mask, u32 init_value1,
72				 u32 init_value2, u32 num_iter,
73				 enum hws_pattern pattern,
74				 enum hws_edge_compare edge_comp,
75				 enum hws_ddr_cs train_cs_type, u32 cs_num,
76				 enum hws_training_ip_stat *train_status);
77u8 mv_ddr_tip_sub_phy_byte_status_get(u32 if_id, u32 subphy_id);
78void mv_ddr_tip_sub_phy_byte_status_set(u32 if_id, u32 subphy_id, u8 byte_status_data);
79void ddr3_tip_print_bist_res(void);
80struct pattern_info *ddr3_tip_get_pattern_table(void);
81u16 *ddr3_tip_get_mask_results_dq_reg(void);
82u16 *ddr3_tip_get_mask_results_pup_reg_map(void);
83int mv_ddr_load_dm_pattern_to_odpg(enum hws_access_type access_type, enum hws_pattern pattern,
84				   enum dm_direction dm_dir);
85int mv_ddr_pattern_start_addr_set(struct pattern_info *pattern_tbl, enum hws_pattern pattern, u32 addr);
86#endif /* _DDR3_TRAINING_IP_ENGINE_H_ */
87