| /u-boot/drivers/i2c/ |
| H A D | davinci_i2c.c | 34 REG(&(i2c_base->i2c_con)) = 0;\
39 static int _wait_for_bus(struct i2c_regs *i2c_base) argument
43 REG(&(i2c_base->i2c_stat)) = 0xffff;
46 stat = REG(&(i2c_base->i2c_stat));
48 REG(&(i2c_base->i2c_stat)) = 0xffff;
52 REG(&(i2c_base->i2c_stat)) = stat;
56 REG(&(i2c_base->i2c_stat)) = 0xffff;
60 static int _poll_i2c_irq(struct i2c_regs *i2c_base, int mask) argument
66 stat = REG(&(i2c_base->i2c_stat));
71 REG(&(i2c_base
75 _flush_rx(struct i2c_regs *i2c_base) argument
87 _davinci_i2c_setspeed(struct i2c_regs *i2c_base, uint speed) argument
102 _davinci_i2c_init(struct i2c_regs *i2c_base, uint speed, int slaveadd) argument
125 _davinci_i2c_read(struct i2c_regs *i2c_base, uint8_t chip, uint32_t addr, int alen, uint8_t *buf, int len) argument
223 _davinci_i2c_write(struct i2c_regs *i2c_base, uint8_t chip, uint32_t addr, int alen, uint8_t *buf, int len) argument
305 _davinci_i2c_probe_chip(struct i2c_regs *i2c_base, uint8_t chip) argument
[all...] |
| H A D | designware_i2c.c | 38 static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) argument
44 writel(ena, &i2c_base->ic_enable);
45 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
212 * @i2c_base: Registers for the I2C controller
282 * @i2c_base: Registers for the I2C controller
287 static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base, argument
295 ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config);
300 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B;
303 dw_i2c_enable(i2c_base, false);
305 cntl = (readl(&i2c_base
372 i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr) argument
388 i2c_flush_rxfifo(struct i2c_regs *i2c_base) argument
399 i2c_wait_for_bb(struct i2c_regs *i2c_base) argument
414 i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr, int alen) argument
430 i2c_xfer_finish(struct i2c_regs *i2c_base) argument
463 __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, int alen, u8 *buffer, int len) argument
531 __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr, int alen, u8 *buffer, int len) argument
587 __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) argument
670 struct i2c_regs *i2c_base = i2c_get_base(adap); local
[all...] |
| H A D | omap24xx_i2c.c | 223 static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay) argument
233 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
235 while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) &
237 omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG);
247 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
255 static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay) argument
265 status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg);
278 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
285 static void flush_fifo(void __iomem *i2c_base, int ip_rev) argument
294 stat = omap_i2c_read_reg(i2c_base, ip_re
305 __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed, int *waitdelay) argument
372 omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev) argument
420 __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed, int slaveadd, int *waitdelay) argument
483 __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay, uchar chip) argument
552 __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay, uchar chip, uint addr, int alen, uchar *buffer, int len) argument
706 __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay, uchar chip, uint addr, int alen, uchar *buffer, int len) argument
889 void __iomem *i2c_base = omap24_get_base(adap); local
899 void __iomem *i2c_base = omap24_get_base(adap); local
908 void __iomem *i2c_base = omap24_get_base(adap); local
925 void __iomem *i2c_base = omap24_get_base(adap); local
934 void __iomem *i2c_base = omap24_get_base(adap); local
[all...] |
| H A D | fsl_i2c.c | 50 static const struct fsl_i2c_base *i2c_base[4] = { variable in typeref:struct:fsl_i2c_base
504 __i2c_init(i2c_base[adap->hwadapnr], speed, slaveadd,
510 return __i2c_probe_chip(i2c_base[adap->hwadapnr], chip);
518 return __i2c_read(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
527 return __i2c_write(i2c_base[adap->hwadapnr], chip_addr, &o[4 - olen],
533 return __i2c_set_bus_speed(i2c_base[adap->hwadapnr], speed,
|
| /u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | spl.h | 55 u32 i2c_base; /* i2c base address */ member in struct:spl_machine_param
|
| /u-boot/board/samsung/arndale/ |
| H A D | arndale_spl.c | 36 .i2c_base = 0x12c60000,
|
| /u-boot/board/samsung/smdk5250/ |
| H A D | smdk5250_spl.c | 38 .i2c_base = 0x12c60000,
|
| /u-boot/board/samsung/smdk5420/ |
| H A D | smdk5420_spl.c | 38 .i2c_base = 0x12c60000,
|