1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2009 4 * Vipin Kumar, STMicroelectronics, vipin.kumar@st.com. 5 */ 6 7#include <common.h> 8#include <clk.h> 9#include <dm.h> 10#include <i2c.h> 11#include <log.h> 12#include <malloc.h> 13#include <pci.h> 14#include <reset.h> 15#include <asm/io.h> 16#include <linux/delay.h> 17#include "designware_i2c.h" 18#include <dm/device_compat.h> 19#include <linux/err.h> 20 21/* 22 * This assigned unique hex value is constant and is derived from the two ASCII 23 * letters 'DW' followed by a 16-bit unsigned number 24 */ 25#define DW_I2C_COMP_TYPE 0x44570140 26 27/* 28 * This constant is used to calculate when during the clock high phase the data 29 * bit shall be read. The value was copied from the Linux v6.5 function 30 * i2c_dw_scl_hcnt() which provides the following explanation: 31 * 32 * "This is just an experimental rule: the tHD;STA period turned out to be 33 * proportinal to (_HCNT + 3). With this setting, we could meet both tHIGH and 34 * tHD;STA timing specs." 35 */ 36#define T_HD_STA_OFFSET 3 37 38static int dw_i2c_enable(struct i2c_regs *i2c_base, bool enable) 39{ 40 u32 ena = enable ? IC_ENABLE_0B : 0; 41 int timeout = 100; 42 43 do { 44 writel(ena, &i2c_base->ic_enable); 45 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena) 46 return 0; 47 48 /* 49 * Wait 10 times the signaling period of the highest I2C 50 * transfer supported by the driver (for 400KHz this is 51 * 25us) as described in the DesignWare I2C databook. 52 */ 53 udelay(25); 54 } while (timeout--); 55 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis"); 56 57 return -ETIMEDOUT; 58} 59 60/* High and low times in different speed modes (in ns) */ 61enum { 62 /* SDA Hold Time */ 63 DEFAULT_SDA_HOLD_TIME = 300, 64}; 65 66/** 67 * calc_counts() - Convert a period to a number of IC clk cycles 68 * 69 * @ic_clk: Input clock in Hz 70 * @period_ns: Period to represent, in ns 71 * Return: calculated count 72 */ 73static uint calc_counts(uint ic_clk, uint period_ns) 74{ 75 return DIV_ROUND_UP(ic_clk / 1000 * period_ns, NANO_TO_KILO); 76} 77 78/** 79 * struct i2c_mode_info - Information about an I2C speed mode 80 * 81 * Each speed mode has its own characteristics. This struct holds these to aid 82 * calculations in dw_i2c_calc_timing(). 83 * 84 * @speed: Speed in Hz 85 * @min_scl_lowtime_ns: Minimum value for SCL low period in ns 86 * @min_scl_hightime_ns: Minimum value for SCL high period in ns 87 * @def_rise_time_ns: Default rise time in ns 88 * @def_fall_time_ns: Default fall time in ns 89 */ 90struct i2c_mode_info { 91 int speed; 92 int min_scl_hightime_ns; 93 int min_scl_lowtime_ns; 94 int def_rise_time_ns; 95 int def_fall_time_ns; 96}; 97 98static const struct i2c_mode_info info_for_mode[] = { 99 [IC_SPEED_MODE_STANDARD] = { 100 I2C_SPEED_STANDARD_RATE, 101 MIN_SS_SCL_HIGHTIME, 102 MIN_SS_SCL_LOWTIME, 103 1000, 104 300, 105 }, 106 [IC_SPEED_MODE_FAST] = { 107 I2C_SPEED_FAST_RATE, 108 MIN_FS_SCL_HIGHTIME, 109 MIN_FS_SCL_LOWTIME, 110 300, 111 300, 112 }, 113 [IC_SPEED_MODE_FAST_PLUS] = { 114 I2C_SPEED_FAST_PLUS_RATE, 115 MIN_FP_SCL_HIGHTIME, 116 MIN_FP_SCL_LOWTIME, 117 260, 118 500, 119 }, 120 [IC_SPEED_MODE_HIGH] = { 121 I2C_SPEED_HIGH_RATE, 122 MIN_HS_SCL_HIGHTIME, 123 MIN_HS_SCL_LOWTIME, 124 120, 125 120, 126 }, 127}; 128 129/** 130 * dw_i2c_calc_timing() - Calculate the timings to use for a bus 131 * 132 * @priv: Bus private information (NULL if not using driver model) 133 * @mode: Speed mode to use 134 * @ic_clk: IC clock speed in Hz 135 * @spk_cnt: Spike-suppression count 136 * @config: Returns value to use 137 * Return: 0 if OK, -EINVAL if the calculation failed due to invalid data 138 */ 139static int dw_i2c_calc_timing(struct dw_i2c *priv, enum i2c_speed_mode mode, 140 int ic_clk, int spk_cnt, 141 struct dw_i2c_speed_config *config) 142{ 143 int fall_cnt, rise_cnt, min_tlow_cnt, min_thigh_cnt; 144 int hcnt, lcnt, period_cnt, diff, tot; 145 int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns; 146 const struct i2c_mode_info *info; 147 148 /* 149 * Find the period, rise, fall, min tlow, and min thigh in terms of 150 * counts of the IC clock 151 */ 152 info = &info_for_mode[mode]; 153 period_cnt = ic_clk / info->speed; 154 scl_rise_time_ns = priv && priv->scl_rise_time_ns ? 155 priv->scl_rise_time_ns : info->def_rise_time_ns; 156 scl_fall_time_ns = priv && priv->scl_fall_time_ns ? 157 priv->scl_fall_time_ns : info->def_fall_time_ns; 158 rise_cnt = calc_counts(ic_clk, scl_rise_time_ns); 159 fall_cnt = calc_counts(ic_clk, scl_fall_time_ns); 160 min_tlow_cnt = calc_counts(ic_clk, info->min_scl_lowtime_ns); 161 min_thigh_cnt = calc_counts(ic_clk, info->min_scl_hightime_ns); 162 163 debug("dw_i2c: mode %d, ic_clk %d, speed %d, period %d rise %d fall %d tlow %d thigh %d spk %d\n", 164 mode, ic_clk, info->speed, period_cnt, rise_cnt, fall_cnt, 165 min_tlow_cnt, min_thigh_cnt, spk_cnt); 166 167 /* 168 * Back-solve for hcnt and lcnt according to the following equations: 169 * SCL_High_time = [(HCNT + IC_*_SPKLEN + T_HD_STA_OFFSET) * ic_clk] + SCL_Fall_time 170 * SCL_Low_time = [(LCNT + 1) * ic_clk] - SCL_Fall_time + SCL_Rise_time 171 */ 172 hcnt = min_thigh_cnt - fall_cnt - T_HD_STA_OFFSET - spk_cnt; 173 lcnt = min_tlow_cnt - rise_cnt + fall_cnt - 1; 174 175 if (hcnt < 0 || lcnt < 0) { 176 debug("dw_i2c: bad counts. hcnt = %d lcnt = %d\n", hcnt, lcnt); 177 return log_msg_ret("counts", -EINVAL); 178 } 179 180 /* 181 * Now add things back up to ensure the period is hit. If it is off, 182 * split the difference and bias to lcnt for remainder 183 */ 184 tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1; 185 186 if (tot < period_cnt) { 187 diff = (period_cnt - tot) / 2; 188 hcnt += diff; 189 lcnt += diff; 190 tot = hcnt + lcnt + T_HD_STA_OFFSET + spk_cnt + rise_cnt + 1; 191 lcnt += period_cnt - tot; 192 } 193 194 config->scl_lcnt = lcnt; 195 config->scl_hcnt = hcnt; 196 197 /* Use internal default unless other value is specified */ 198 sda_hold_time_ns = priv && priv->sda_hold_time_ns ? 199 priv->sda_hold_time_ns : DEFAULT_SDA_HOLD_TIME; 200 config->sda_hold = calc_counts(ic_clk, sda_hold_time_ns); 201 202 debug("dw_i2c: hcnt = %d lcnt = %d sda hold = %d\n", hcnt, lcnt, 203 config->sda_hold); 204 205 return 0; 206} 207 208/** 209 * calc_bus_speed() - Calculate the config to use for a particular i2c speed 210 * 211 * @priv: Private information for the driver (NULL if not using driver model) 212 * @i2c_base: Registers for the I2C controller 213 * @speed: Required i2c speed in Hz 214 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK) 215 * @config: Returns the config to use for this speed 216 * Return: 0 if OK, -ve on error 217 */ 218static int calc_bus_speed(struct dw_i2c *priv, struct i2c_regs *regs, int speed, 219 ulong bus_clk, struct dw_i2c_speed_config *config) 220{ 221 const struct dw_scl_sda_cfg *scl_sda_cfg = NULL; 222 enum i2c_speed_mode i2c_spd; 223 int spk_cnt; 224 int ret; 225 226 if (priv) 227 scl_sda_cfg = priv->scl_sda_cfg; 228 /* Allow high speed if there is no config, or the config allows it */ 229 if (speed >= I2C_SPEED_HIGH_RATE) 230 i2c_spd = IC_SPEED_MODE_HIGH; 231 else if (speed >= I2C_SPEED_FAST_PLUS_RATE) 232 i2c_spd = IC_SPEED_MODE_FAST_PLUS; 233 else if (speed >= I2C_SPEED_FAST_RATE) 234 i2c_spd = IC_SPEED_MODE_FAST; 235 else 236 i2c_spd = IC_SPEED_MODE_STANDARD; 237 238 /* Check is high speed possible and fall back to fast mode if not */ 239 if (i2c_spd == IC_SPEED_MODE_HIGH) { 240 u32 comp_param1; 241 242 comp_param1 = readl(®s->comp_param1); 243 if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK) 244 != DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) 245 i2c_spd = IC_SPEED_MODE_FAST; 246 } 247 248 /* Get the proper spike-suppression count based on target speed */ 249 if (!priv || !priv->has_spk_cnt) 250 spk_cnt = 0; 251 else if (i2c_spd >= IC_SPEED_MODE_HIGH) 252 spk_cnt = readl(®s->hs_spklen); 253 else 254 spk_cnt = readl(®s->fs_spklen); 255 if (scl_sda_cfg) { 256 config->sda_hold = scl_sda_cfg->sda_hold; 257 if (i2c_spd == IC_SPEED_MODE_STANDARD) { 258 config->scl_hcnt = scl_sda_cfg->ss_hcnt; 259 config->scl_lcnt = scl_sda_cfg->ss_lcnt; 260 } else if (i2c_spd == IC_SPEED_MODE_HIGH) { 261 config->scl_hcnt = scl_sda_cfg->hs_hcnt; 262 config->scl_lcnt = scl_sda_cfg->hs_lcnt; 263 } else { 264 config->scl_hcnt = scl_sda_cfg->fs_hcnt; 265 config->scl_lcnt = scl_sda_cfg->fs_lcnt; 266 } 267 } else { 268 ret = dw_i2c_calc_timing(priv, i2c_spd, bus_clk, spk_cnt, 269 config); 270 if (ret) 271 return log_msg_ret("gen_confg", ret); 272 } 273 config->speed_mode = i2c_spd; 274 275 return 0; 276} 277 278/** 279 * _dw_i2c_set_bus_speed() - Set the i2c speed 280 * 281 * @priv: Private information for the driver (NULL if not using driver model) 282 * @i2c_base: Registers for the I2C controller 283 * @speed: Required i2c speed in Hz 284 * @bus_clk: Input clock to the I2C controller in Hz (e.g. IC_CLK) 285 * Return: 0 if OK, -ve on error 286 */ 287static int _dw_i2c_set_bus_speed(struct dw_i2c *priv, struct i2c_regs *i2c_base, 288 unsigned int speed, unsigned int bus_clk) 289{ 290 struct dw_i2c_speed_config config; 291 unsigned int cntl; 292 unsigned int ena; 293 int ret; 294 295 ret = calc_bus_speed(priv, i2c_base, speed, bus_clk, &config); 296 if (ret) 297 return ret; 298 299 /* Get enable setting for restore later */ 300 ena = readl(&i2c_base->ic_enable) & IC_ENABLE_0B; 301 302 /* to set speed cltr must be disabled */ 303 dw_i2c_enable(i2c_base, false); 304 305 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK)); 306 307 switch (config.speed_mode) { 308 case IC_SPEED_MODE_HIGH: 309 cntl |= IC_CON_SPD_HS; 310 writel(config.scl_hcnt, &i2c_base->ic_hs_scl_hcnt); 311 writel(config.scl_lcnt, &i2c_base->ic_hs_scl_lcnt); 312 break; 313 case IC_SPEED_MODE_STANDARD: 314 cntl |= IC_CON_SPD_SS; 315 writel(config.scl_hcnt, &i2c_base->ic_ss_scl_hcnt); 316 writel(config.scl_lcnt, &i2c_base->ic_ss_scl_lcnt); 317 break; 318 case IC_SPEED_MODE_FAST_PLUS: 319 case IC_SPEED_MODE_FAST: 320 default: 321 cntl |= IC_CON_SPD_FS; 322 writel(config.scl_hcnt, &i2c_base->ic_fs_scl_hcnt); 323 writel(config.scl_lcnt, &i2c_base->ic_fs_scl_lcnt); 324 break; 325 } 326 327 writel(cntl, &i2c_base->ic_con); 328 329 /* Configure SDA Hold Time if required */ 330 if (config.sda_hold) 331 writel(config.sda_hold, &i2c_base->ic_sda_hold); 332 333 /* Restore back i2c now speed set */ 334 if (ena == IC_ENABLE_0B) 335 dw_i2c_enable(i2c_base, true); 336 if (priv) 337 priv->config = config; 338 339 return 0; 340} 341 342int dw_i2c_gen_speed_config(const struct udevice *dev, int speed_hz, 343 struct dw_i2c_speed_config *config) 344{ 345 struct dw_i2c *priv = dev_get_priv(dev); 346 ulong rate; 347 int ret; 348 349#if CONFIG_IS_ENABLED(CLK) 350 rate = clk_get_rate(&priv->clk); 351 if (IS_ERR_VALUE(rate)) 352 return log_msg_ret("clk", -EINVAL); 353#else 354 rate = IC_CLK; 355#endif 356 357 ret = calc_bus_speed(priv, priv->regs, speed_hz, rate, config); 358 if (ret) 359 printf("%s: ret=%d\n", __func__, ret); 360 if (ret) 361 return log_msg_ret("calc_bus_speed", ret); 362 363 return 0; 364} 365 366/* 367 * i2c_setaddress - Sets the target slave address 368 * @i2c_addr: target i2c address 369 * 370 * Sets the target slave address. 371 */ 372static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr) 373{ 374 /* Disable i2c */ 375 dw_i2c_enable(i2c_base, false); 376 377 writel(i2c_addr, &i2c_base->ic_tar); 378 379 /* Enable i2c */ 380 dw_i2c_enable(i2c_base, true); 381} 382 383/* 384 * i2c_flush_rxfifo - Flushes the i2c RX FIFO 385 * 386 * Flushes the i2c RX FIFO 387 */ 388static void i2c_flush_rxfifo(struct i2c_regs *i2c_base) 389{ 390 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) 391 readl(&i2c_base->ic_cmd_data); 392} 393 394/* 395 * i2c_wait_for_bb - Waits for bus busy 396 * 397 * Waits for bus busy 398 */ 399static int i2c_wait_for_bb(struct i2c_regs *i2c_base) 400{ 401 unsigned long start_time_bb = get_timer(0); 402 403 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) || 404 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) { 405 406 /* Evaluate timeout */ 407 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB)) 408 return 1; 409 } 410 411 return 0; 412} 413 414static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr, 415 int alen) 416{ 417 if (i2c_wait_for_bb(i2c_base)) 418 return 1; 419 420 i2c_setaddress(i2c_base, chip); 421 while (alen) { 422 alen--; 423 /* high byte address going out first */ 424 writel((addr >> (alen * 8)) & 0xff, 425 &i2c_base->ic_cmd_data); 426 } 427 return 0; 428} 429 430static int i2c_xfer_finish(struct i2c_regs *i2c_base) 431{ 432 ulong start_stop_det = get_timer(0); 433 434 while (1) { 435 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) { 436 readl(&i2c_base->ic_clr_stop_det); 437 break; 438 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) { 439 break; 440 } 441 } 442 443 if (i2c_wait_for_bb(i2c_base)) { 444 printf("Timed out waiting for bus\n"); 445 return 1; 446 } 447 448 i2c_flush_rxfifo(i2c_base); 449 450 return 0; 451} 452 453/* 454 * i2c_read - Read from i2c memory 455 * @chip: target i2c address 456 * @addr: address to read from 457 * @alen: 458 * @buffer: buffer for read data 459 * @len: no of bytes to be read 460 * 461 * Read from i2c memory. 462 */ 463static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr, 464 int alen, u8 *buffer, int len) 465{ 466 unsigned long start_time_rx; 467 unsigned int active = 0; 468 469#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 470 /* 471 * EEPROM chips that implement "address overflow" are ones 472 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 473 * address and the extra bits end up in the "chip address" 474 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 475 * four 256 byte chips. 476 * 477 * Note that we consider the length of the address field to 478 * still be one byte because the extra address bits are 479 * hidden in the chip address. 480 */ 481 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 482 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 483 484 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 485 addr); 486#endif 487 488 if (i2c_xfer_init(i2c_base, dev, addr, alen)) 489 return 1; 490 491 start_time_rx = get_timer(0); 492 while (len) { 493 if (!active) { 494 /* 495 * Avoid writing to ic_cmd_data multiple times 496 * in case this loop spins too quickly and the 497 * ic_status RFNE bit isn't set after the first 498 * write. Subsequent writes to ic_cmd_data can 499 * trigger spurious i2c transfer. 500 */ 501 if (len == 1) 502 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data); 503 else 504 writel(IC_CMD, &i2c_base->ic_cmd_data); 505 active = 1; 506 } 507 508 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) { 509 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data); 510 len--; 511 start_time_rx = get_timer(0); 512 active = 0; 513 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) { 514 return 1; 515 } 516 } 517 518 return i2c_xfer_finish(i2c_base); 519} 520 521/* 522 * i2c_write - Write to i2c memory 523 * @chip: target i2c address 524 * @addr: address to read from 525 * @alen: 526 * @buffer: buffer for read data 527 * @len: no of bytes to be read 528 * 529 * Write to i2c memory. 530 */ 531static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr, 532 int alen, u8 *buffer, int len) 533{ 534 int nb = len; 535 unsigned long start_time_tx; 536 537#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 538 /* 539 * EEPROM chips that implement "address overflow" are ones 540 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 541 * address and the extra bits end up in the "chip address" 542 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 543 * four 256 byte chips. 544 * 545 * Note that we consider the length of the address field to 546 * still be one byte because the extra address bits are 547 * hidden in the chip address. 548 */ 549 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 550 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8)); 551 552 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev, 553 addr); 554#endif 555 556 if (i2c_xfer_init(i2c_base, dev, addr, alen)) 557 return 1; 558 559 start_time_tx = get_timer(0); 560 while (len) { 561 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) { 562 if (--len == 0) { 563 writel(*buffer | IC_STOP, 564 &i2c_base->ic_cmd_data); 565 } else { 566 writel(*buffer, &i2c_base->ic_cmd_data); 567 } 568 buffer++; 569 start_time_tx = get_timer(0); 570 571 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) { 572 printf("Timed out. i2c write Failed\n"); 573 return 1; 574 } 575 } 576 577 return i2c_xfer_finish(i2c_base); 578} 579 580/* 581 * __dw_i2c_init - Init function 582 * @speed: required i2c speed 583 * @slaveaddr: slave address for the device 584 * 585 * Initialization function. 586 */ 587static int __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr) 588{ 589 int ret; 590 591 /* Disable i2c */ 592 ret = dw_i2c_enable(i2c_base, false); 593 if (ret) 594 return ret; 595 596 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM, 597 &i2c_base->ic_con); 598 writel(IC_RX_TL, &i2c_base->ic_rx_tl); 599 writel(IC_TX_TL, &i2c_base->ic_tx_tl); 600 writel(IC_STOP_DET, &i2c_base->ic_intr_mask); 601#if !CONFIG_IS_ENABLED(DM_I2C) 602 _dw_i2c_set_bus_speed(NULL, i2c_base, speed, IC_CLK); 603 writel(slaveaddr, &i2c_base->ic_sar); 604#endif 605 606 /* Enable i2c */ 607 ret = dw_i2c_enable(i2c_base, true); 608 if (ret) 609 return ret; 610 611 return 0; 612} 613 614#if !CONFIG_IS_ENABLED(DM_I2C) 615/* 616 * The legacy I2C functions. These need to get removed once 617 * all users of this driver are converted to DM. 618 */ 619static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap) 620{ 621 switch (adap->hwadapnr) { 622#if CONFIG_SYS_I2C_BUS_MAX >= 4 623 case 3: 624 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3; 625#endif 626#if CONFIG_SYS_I2C_BUS_MAX >= 3 627 case 2: 628 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2; 629#endif 630#if CONFIG_SYS_I2C_BUS_MAX >= 2 631 case 1: 632 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1; 633#endif 634 case 0: 635 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE; 636 default: 637 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr); 638 } 639 640 return NULL; 641} 642 643static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap, 644 unsigned int speed) 645{ 646 adap->speed = speed; 647 return _dw_i2c_set_bus_speed(NULL, i2c_get_base(adap), speed, IC_CLK); 648} 649 650static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 651{ 652 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr); 653} 654 655static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr, 656 int alen, u8 *buffer, int len) 657{ 658 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len); 659} 660 661static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr, 662 int alen, u8 *buffer, int len) 663{ 664 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len); 665} 666 667/* dw_i2c_probe - Probe the i2c chip */ 668static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev) 669{ 670 struct i2c_regs *i2c_base = i2c_get_base(adap); 671 u32 tmp; 672 int ret; 673 674 /* 675 * Try to read the first location of the chip. 676 */ 677 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1); 678 if (ret) 679 dw_i2c_init(adap, adap->speed, adap->slaveaddr); 680 681 return ret; 682} 683 684U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read, 685 dw_i2c_write, dw_i2c_set_bus_speed, 686 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0) 687 688#else /* CONFIG_DM_I2C */ 689/* The DM I2C functions */ 690 691static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 692 int nmsgs) 693{ 694 struct dw_i2c *i2c = dev_get_priv(bus); 695 int ret; 696 697 debug("i2c_xfer: %d messages\n", nmsgs); 698 for (; nmsgs > 0; nmsgs--, msg++) { 699 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 700 if (msg->flags & I2C_M_RD) { 701 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0, 702 msg->buf, msg->len); 703 } else { 704 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0, 705 msg->buf, msg->len); 706 } 707 if (ret) { 708 debug("i2c_write: error sending\n"); 709 return -EREMOTEIO; 710 } 711 } 712 713 return 0; 714} 715 716static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 717{ 718 struct dw_i2c *i2c = dev_get_priv(bus); 719 ulong rate; 720 721#if CONFIG_IS_ENABLED(CLK) 722 rate = clk_get_rate(&i2c->clk); 723 if (IS_ERR_VALUE(rate)) 724 return log_ret(-EINVAL); 725#else 726 rate = IC_CLK; 727#endif 728 return _dw_i2c_set_bus_speed(i2c, i2c->regs, speed, rate); 729} 730 731static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr, 732 uint chip_flags) 733{ 734 struct dw_i2c *i2c = dev_get_priv(bus); 735 struct i2c_regs *i2c_base = i2c->regs; 736 u32 tmp; 737 int ret; 738 739 /* Try to read the first location of the chip */ 740 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1); 741 if (ret) 742 __dw_i2c_init(i2c_base, 0, 0); 743 744 return ret; 745} 746 747int designware_i2c_of_to_plat(struct udevice *bus) 748{ 749 struct dw_i2c *priv = dev_get_priv(bus); 750 int ret; 751 752 if (!priv->regs) 753 priv->regs = dev_read_addr_ptr(bus); 754 dev_read_u32(bus, "i2c-scl-rising-time-ns", &priv->scl_rise_time_ns); 755 dev_read_u32(bus, "i2c-scl-falling-time-ns", &priv->scl_fall_time_ns); 756 dev_read_u32(bus, "i2c-sda-hold-time-ns", &priv->sda_hold_time_ns); 757 758 ret = reset_get_bulk(bus, &priv->resets); 759 if (ret) { 760 if (ret != -ENOTSUPP) 761 dev_warn(bus, "Can't get reset: %d\n", ret); 762 } else { 763 reset_deassert_bulk(&priv->resets); 764 } 765 766#if CONFIG_IS_ENABLED(CLK) 767 ret = clk_get_by_index(bus, 0, &priv->clk); 768 if (ret) 769 return ret; 770 771 ret = clk_enable(&priv->clk); 772 if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { 773 dev_err(bus, "failed to enable clock\n"); 774 return ret; 775 } 776#endif 777 778 return 0; 779} 780 781int designware_i2c_probe(struct udevice *bus) 782{ 783 struct dw_i2c *priv = dev_get_priv(bus); 784 uint comp_type; 785 786 comp_type = readl(&priv->regs->comp_type); 787 if (comp_type != DW_I2C_COMP_TYPE) { 788 log_err("I2C bus %s has unknown type %#x\n", bus->name, 789 comp_type); 790 return -ENXIO; 791 } 792 793 log_debug("I2C bus %s version %#x\n", bus->name, 794 readl(&priv->regs->comp_version)); 795 796 return __dw_i2c_init(priv->regs, 0, 0); 797} 798 799int designware_i2c_remove(struct udevice *dev) 800{ 801 struct dw_i2c *priv = dev_get_priv(dev); 802 803#if CONFIG_IS_ENABLED(CLK) 804 clk_disable(&priv->clk); 805#endif 806 807 return reset_release_bulk(&priv->resets); 808} 809 810const struct dm_i2c_ops designware_i2c_ops = { 811 .xfer = designware_i2c_xfer, 812 .probe_chip = designware_i2c_probe_chip, 813 .set_bus_speed = designware_i2c_set_bus_speed, 814}; 815 816static const struct udevice_id designware_i2c_ids[] = { 817 { .compatible = "snps,designware-i2c" }, 818 { } 819}; 820 821U_BOOT_DRIVER(i2c_designware) = { 822 .name = "i2c_designware", 823 .id = UCLASS_I2C, 824 .of_match = designware_i2c_ids, 825 .of_to_plat = designware_i2c_of_to_plat, 826 .probe = designware_i2c_probe, 827 .priv_auto = sizeof(struct dw_i2c), 828 .remove = designware_i2c_remove, 829 .flags = DM_FLAG_OS_PREPARE, 830 .ops = &designware_i2c_ops, 831}; 832 833#endif /* CONFIG_DM_I2C */ 834