| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3036.c | 46 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); variable in typeref:struct:pll_div
96 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk322x.c | 44 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); variable in typeref:struct:pll_div
98 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3128.c | 39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); variable in typeref:struct:pll_div
157 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3066.c | 81 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); variable in typeref:struct:pll_div
423 rk3066_clk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3188.c | 85 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); variable in typeref:struct:pll_div
389 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
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| H A D | clk_rk3368.c | 58 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 2); variable in typeref:struct:pll_div
146 rkclk_set_pll(cru, GPLL, &gpll_init_cfg);
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| H A D | clk_rv1108.c | 46 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); variable in typeref:struct:pll_div
648 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3288.c | 147 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); variable in typeref:struct:pll_div
440 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3328.c | 41 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 1, 4, 1); variable in typeref:struct:pll_div
296 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
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| H A D | clk_rk3399.c | 57 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1); variable in typeref:struct:pll_div
1396 rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
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