| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3288.c | 393 static ulong rockchip_i2s_get_clk(struct rockchip_cru *cru, uint gclk_rate) argument
403 rate = (unsigned long long)gclk_rate * n;
409 static ulong rockchip_i2s_set_clk(struct rockchip_cru *cru, uint gclk_rate, argument
416 v = rockchip_clk_gcd(gclk_rate, freq);
417 n = gclk_rate / v;
419 assert(freq == gclk_rate / n * d);
423 return rockchip_i2s_get_clk(cru, gclk_rate);
576 static ulong rockchip_mmc_get_clk(struct rockchip_cru *cru, uint gclk_rate, argument
606 src_rate = mux == EMMC_PLL_SELECT_24MHZ ? OSC_HZ : gclk_rate;
610 static ulong rockchip_mmc_set_clk(struct rockchip_cru *cru, uint gclk_rate, argument
660 rockchip_spi_get_clk(struct rockchip_cru *cru, uint gclk_rate, int periph) argument
690 rockchip_spi_set_clk(struct rockchip_cru *cru, uint gclk_rate, int periph, uint freq) argument
752 ulong new_rate, gclk_rate; local
796 ulong new_rate, gclk_rate; local
[all...] |
| H A D | clk_rk3066.c | 253 static ulong rk3066_clk_mmc_get_clk(struct rk3066_cru *cru, uint gclk_rate, argument
279 return DIV_TO_RATE(gclk_rate, div) / 2;
282 static ulong rk3066_clk_mmc_set_clk(struct rk3066_cru *cru, uint gclk_rate, argument
287 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
289 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
315 return rk3066_clk_mmc_get_clk(cru, gclk_rate, periph);
318 static ulong rk3066_clk_spi_get_clk(struct rk3066_cru *cru, uint gclk_rate, argument
337 return DIV_TO_RATE(gclk_rate, div);
340 static ulong rk3066_clk_spi_set_clk(struct rk3066_cru *cru, uint gclk_rate, argument
498 ulong new_rate, gclk_rate; local
[all...] |
| H A D | clk_rk3188.c | 262 static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, argument
288 return DIV_TO_RATE(gclk_rate, div) / 2;
291 static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, argument
296 debug("%s: gclk_rate=%u\n", __func__, gclk_rate);
298 src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1;
324 return rockchip_mmc_get_clk(cru, gclk_rate, periph);
327 static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate, argument
346 return DIV_TO_RATE(gclk_rate, div);
349 static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, argument
465 ulong new_rate, gclk_rate; local
[all...] |
| H A D | clk_rk322x.c | 357 ulong rate, gclk_rate; local
359 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
368 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
380 ulong new_rate, gclk_rate; local
382 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
388 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
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| H A D | clk_rk3036.c | 298 ulong new_rate, gclk_rate; local
300 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
306 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
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| H A D | clk_rk3128.c | 511 ulong new_rate, gclk_rate; local
513 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
524 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
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