| /u-boot/drivers/pci/ |
| H A D | pcie_dw_ti.c | 64 struct pcie_dw dw; member in struct:pcie_dw_ti
87 dw_pcie_dbi_write_enable(&pci->dw, true);
89 val = readl(pci->dw.dbi_base + PCIE_LINK_CAPABILITY);
92 writel(val, pci->dw.dbi_base + PCIE_LINK_CAPABILITY);
94 val = readl(pci->dw.dbi_base + PCIE_LINK_CTL_2);
97 writel(val, pci->dw.dbi_base + PCIE_LINK_CTL_2);
99 dw_pcie_dbi_write_enable(&pci->dw, false);
113 val = readl(pci->dw.dbi_base + PCIE_PORT_DEBUG0);
177 syscon = syscon_regmap_lookup_by_phandle(pci->dw.dev,
192 dev_err(pci->dw
[all...] |
| H A D | pcie_dw_imx.c | 50 struct pcie_dw dw; member in struct:pcie_dw_imx
73 dw_pcie_dbi_write_enable(&priv->dw, true);
75 clrsetbits_le32(priv->dw.dbi_base + PCIE_LINK_CAPABILITY,
78 dw_pcie_dbi_write_enable(&priv->dw, false);
101 return readl_poll_sleep_timeout(priv->dw.dbi_base + PCIE_PORT_DEBUG1,
209 priv->dw.first_busno = dev_seq(dev);
210 priv->dw.dev = dev;
211 pcie_dw_setup_host(&priv->dw);
220 pcie_dw_get_link_speed(&priv->dw),
221 pcie_dw_get_link_width(&priv->dw),
[all...] |
| H A D | pcie_dw_meson.c | 47 struct pcie_dw dw; member in struct:meson_pcie
113 dw_pcie_dbi_write_enable(&priv->dw, true);
115 val = readl(priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
120 writel(val, priv->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
122 val = readl(priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
125 writel(val, priv->dw.dbi_base + PCIE_LINK_WIDTH_SPEED_CONTROL);
127 dw_pcie_dbi_write_enable(&priv->dw, false);
225 u16 offset = dm_pci_find_capability(priv->dw.dev, PCI_CAP_ID_EXP);
228 dw_pcie_dbi_write_enable(&priv->dw, true);
230 val = readl(priv->dw
[all...] |
| H A D | pcie_dw_rockchip.c | 39 struct pcie_dw dw; member in struct:rk_pcie
114 dev_err(rk_pcie->dw.dev, "Read APB address failed\n");
126 dev_err(rk_pcie->dw.dev, "Write APB address failed\n");
164 dw_pcie_dbi_write_enable(&pci->dw, true);
167 writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
169 writel(0, pci->dw.dbi_base + PCIE_TYPE0_HDR_DBI2_OFFSET +
172 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CAPABILITY,
175 clrsetbits_le32(pci->dw.dbi_base + PCIE_LINK_CTL_2,
179 val = readl(pci->dw.dbi_base + PCIE_PORT_LINK_CONTROL);
194 dev_err(pci->dw
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| H A D | pcie_dw_sifive.c | 34 struct pcie_dw dw; member in struct:pcie_sifive
266 val = readl(sv->dw.dbi_base + PHY_DEBUG_R1);
282 val = readl(sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
284 writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
287 linkcap = readl(sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
289 writel(linkcap, sv->dw.dbi_base + PF0_PCIE_CAP_LINK_CAP);
293 writel(val, sv->dw.dbi_base + PCIE_MISC_CONTROL_1);
299 readl(sv->dw.dbi_base + PHY_DEBUG_R0),
300 readl(sv->dw.dbi_base + PHY_DEBUG_R1));
316 val = readl(sv->dw
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| H A D | pcie_intel_fpga.c | 150 u32 dw[4]; local
159 dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
164 dw[count++] = cra_readl(pcie, RP_RXCPL_REG);
166 comp_status = TLP_COMP_STATUS(dw[1]);
173 TLP_BYTE_COUNT(dw[1]) == sizeof(u32) &&
175 *value = dw[3];
|
| /u-boot/drivers/power/acpi_pmc/ |
| H A D | acpi-pmc-uclass.c | 42 u32 *dw; local
50 dw = upriv->gpe0_dw;
55 if (dw[i] & ~mask)
63 if (dw[0] == dw[1] || dw[1] == dw[2]) {
68 dw[i] = gpio_cfg >> gpe0_shift(upriv, i);
72 gpio_cfg |= dw[i] << gpe0_shift(upriv, i);
80 pinctrl_route_gpe(itss, dw[
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| /u-boot/drivers/ddr/fsl/ |
| H A D | main.c | 339 unsigned int dw; local
342 dw = pinfo->dimm_params[i][j].primary_sdram_width;
343 if ((dw == 72 || dw == 64)) {
346 } else if ((dw == 40 || dw == 32)) {
356 unsigned int dw; local
357 dw = pinfo->dimm_params[i][j].data_width;
359 && (dw == 72 || dw
[all...] |
| /u-boot/drivers/timer/ |
| H A D | Makefile | 15 obj-$(CONFIG_DESIGNWARE_APB_TIMER) += dw-apb-timer.o
|
| /u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | sdram.c | 29 u32 dw = DDR_DW32 ? 4 : 2; local
34 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
38 size = (1 << (DDR_ROW + DDR_COL)) * dw * banks;
|
| /u-boot/scripts/ |
| H A D | checkstack.pl | 85 $re = qr/.*st[dw]u.*r1,-($x{1,8})\(r1\)/o;
|
| /u-boot/drivers/video/nexell/soc/ |
| H A D | s5pxx18_soc_mlc.h | 238 u32 dw, u32 dh, int bhlumaenb,
|
| H A D | s5pxx18_soc_mlc.c | 1042 void nx_mlc_set_video_layer_scale(u32 module_index, u32 sw, u32 sh, u32 dw, argument
1054 if ((bhlumaenb || bhchromaenb) && dw > sw) {
1056 dw--;
1058 hscale = (sw << 11) / dw;
|