#
d678a59d |
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18-May-2024 |
Tom Rini <trini@konsulko.com> |
Revert "Merge patch series "arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"" When bringing in the series 'arm: dts: am62-beagleplay: Fix Beagleplay Ethernet"' I failed to notice that b4 noticed it was based on next and so took that as the base commit and merged that part of next to master. This reverts commit c8ffd1356d42223cbb8c86280a083cc3c93e6426, reversing changes made to 2ee6f3a5f7550de3599faef9704e166e5dcace35. Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Tom Rini <trini@konsulko.com> |
#
8691ffa5 |
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24-Apr-2024 |
Greg Malysa <greg.malysa@timesys.com> |
drivers: timer: Add in driver support for ADI SC5XX-family GP timer peripheral Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com> Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Greg Malysa <greg.malysa@timesys.com> |
#
8a0d5f2f |
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28-Sep-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> |
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c202426d |
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19-Sep-2023 |
Kuan Lim Lee <kuanlim.lee@starfivetech.com> |
timer: starfive: Add Starfive timer support Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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9675d920 |
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21-Jun-2023 |
Bin Meng <bmeng@tinylab.org> |
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> |
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2c0bdcac |
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13-Feb-2023 |
Sergei Antonov <saproj@gmail.com> |
timer: fttmr010: return a previously deleted driver now ported to DM The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com> |
#
adf86904 |
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01-Feb-2023 |
Svyatoslav Ryhel <clamor95@gmail.com> |
drivers: timer: add driver for ARMv7 based Tegra devices and T210 Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com> |
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731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
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35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
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b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
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e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
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c316ee67 |
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27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
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#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
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b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
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b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
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e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
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70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
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f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
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11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
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7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
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79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
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ed1b7266 |
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07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
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057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
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4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
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12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
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d3c3606c |
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14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
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d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
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66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
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5120a083 |
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07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
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fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
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18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
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21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
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18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
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24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
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30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
8691ffa5 |
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24-Apr-2024 |
Greg Malysa <greg.malysa@timesys.com> |
drivers: timer: Add in driver support for ADI SC5XX-family GP timer peripheral Co-developed-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Signed-off-by: Nathan Barrett-Morrison <nathan.morrison@timesys.com> Co-developed-by: Angelo Dureghello <angelo.dureghello@timesys.com> Signed-off-by: Angelo Dureghello <angelo.dureghello@timesys.com> Co-developed-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Ian Roberts <ian.roberts@timesys.com> Signed-off-by: Greg Malysa <greg.malysa@timesys.com> |
#
8a0d5f2f |
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28-Sep-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> |
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c202426d |
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19-Sep-2023 |
Kuan Lim Lee <kuanlim.lee@starfivetech.com> |
timer: starfive: Add Starfive timer support Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9675d920 |
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21-Jun-2023 |
Bin Meng <bmeng@tinylab.org> |
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
2c0bdcac |
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13-Feb-2023 |
Sergei Antonov <saproj@gmail.com> |
timer: fttmr010: return a previously deleted driver now ported to DM The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com> |
#
adf86904 |
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01-Feb-2023 |
Svyatoslav Ryhel <clamor95@gmail.com> |
drivers: timer: add driver for ARMv7 based Tegra devices and T210 Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com> |
#
731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
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27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
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11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
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ed1b7266 |
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07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
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057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
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12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
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d3c3606c |
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14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
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2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
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d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
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66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
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07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
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fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
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18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
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21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
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18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
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24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
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30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
8a0d5f2f |
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28-Sep-2023 |
Yu Chien Peter Lin <peterlin@andestech.com> |
riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org> |
#
c202426d |
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19-Sep-2023 |
Kuan Lim Lee <kuanlim.lee@starfivetech.com> |
timer: starfive: Add Starfive timer support Add timer driver in Starfive SoC. It is an timer that outside of CPU core and inside Starfive SoC. Signed-off-by: Kuan Lim Lee <kuanlim.lee@starfivetech.com> Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
9675d920 |
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21-Jun-2023 |
Bin Meng <bmeng@tinylab.org> |
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
2c0bdcac |
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13-Feb-2023 |
Sergei Antonov <saproj@gmail.com> |
timer: fttmr010: return a previously deleted driver now ported to DM The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com> |
#
adf86904 |
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01-Feb-2023 |
Svyatoslav Ryhel <clamor95@gmail.com> |
drivers: timer: add driver for ARMv7 based Tegra devices and T210 Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com> |
#
731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
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27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
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11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
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07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
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12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
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14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
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07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
9675d920 |
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21-Jun-2023 |
Bin Meng <bmeng@tinylab.org> |
riscv: Rename SiFive CLINT to RISC-V ALINT As the RISC-V ACLINT specification is defined to be backward compatible with the SiFive CLINT specification, we rename SiFive CLINT to RISC-V ALINT in the source tree to be future-proof. Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
2c0bdcac |
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13-Feb-2023 |
Sergei Antonov <saproj@gmail.com> |
timer: fttmr010: return a previously deleted driver now ported to DM The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com> |
#
adf86904 |
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01-Feb-2023 |
Svyatoslav Ryhel <clamor95@gmail.com> |
drivers: timer: add driver for ARMv7 based Tegra devices and T210 Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com> |
#
731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
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27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
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11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
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07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
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12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
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14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
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07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
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18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
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21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
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30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
2c0bdcac |
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13-Feb-2023 |
Sergei Antonov <saproj@gmail.com> |
timer: fttmr010: return a previously deleted driver now ported to DM The fttmr010 timer driver was deleted by commit 29fc6f24926e ("ARM: remove a320evb board support") The original source file was: arch/arm/cpu/arm920t/a320/timer.c Return the driver to the codebase in a DM compatible form. A platform using fttmr010 will be submitted later. This hardware is described in the datasheet [1], starting from page 348. According to the datasheet, there is a Revision Register at offset 0x3C, which is not present in 'struct fttmr010'. Add it and debug() print revision in probe function. [1] https://bitbucket.org/Kasreyn/mkrom-uc7112lx/src/master/documents/FIC8120_DS_v1.2.pdf Signed-off-by: Sergei Antonov <saproj@gmail.com> |
#
adf86904 |
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01-Feb-2023 |
Svyatoslav Ryhel <clamor95@gmail.com> |
drivers: timer: add driver for ARMv7 based Tegra devices and T210 Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com> |
#
731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
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27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
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#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
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11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
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07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
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12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
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d3c3606c |
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14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
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d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
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07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
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18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
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21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
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18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
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24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
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30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
adf86904 |
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01-Feb-2023 |
Svyatoslav Ryhel <clamor95@gmail.com> |
drivers: timer: add driver for ARMv7 based Tegra devices and T210 Add timer support for T20/T30/T114/T124 and T210 based devices. Driver is based on DM, has device tree support and can be used on SPL and early boot stage. Arm64 Tegra (apart T210) according to comment in tegra-common.h use architected timer. Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30 Tested-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> # Surface RT T30 Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20 Tested-by: Agneli <poczt@protonmail.ch> # Toshiba AC100 T20 Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30 Co-developed-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Jonas Schwöbel <jonasschwoebel@yahoo.de> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom <twarren@nvidia.com> |
#
731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
|
27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@collabora.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
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11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
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07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
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12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
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14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
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07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
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18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
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21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
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18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
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30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
731d108d |
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20-Oct-2022 |
Andre Przywara <andre.przywara@arm.com> |
timer: add SP804 UCLASS timer driver The "Arm Ltd. Dual-Timer Module (SP804)" is a simple 32-bit count-down timer IP with interrupt functionality, and is used in some SoCs from various vendors. Add a simple DM compliant timer driver, to allow users of the SP804 to switch to DM_TIMER. This relies on the input clock to be accessible via the DM clock framework, which should be fine as we probably look at fixed-clock's here anyway. We re-program the control register in the probe() function, but keep the divider in place, in case this has been set to something on purpose before. The TRM for the timer IP can be found here: https://developer.arm.com/documentation/ddi0271/latest Signed-off-by: Andre Przywara <andre.przywara@arm.com> |
#
35751c7f |
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23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
|
27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
|
24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
|
08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
|
18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
35751c7f |
|
23-Aug-2022 |
William Zhang <william.zhang@broadcom.com> |
timer: sti: convert sti-timer to arm a9 global timer STI timer is actually ARM Cortex A9 global timer. Convert the driver to use generic global timer name and make it consistent with Linux kernel global timer driver. This also allows any A9 based device to use this driver. Signed-off-by: William Zhang <william.zhang@broadcom.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com> |
#
b7e0750d |
|
05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
|
17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
|
27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
|
24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
|
08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
|
18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
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15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
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18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
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16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
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21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
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21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
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18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
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24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
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30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b7e0750d |
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05-Aug-2022 |
Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> |
zynq: Convert arm twd timer to DM driver Move arm twd timer driver from zynq to generic location. DM timer drivers are designed differently to original driver. Timer is counting up and not down. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com> Link: https://lore.kernel.org/r/20220805061629.1207-1-stefan.herbrechtsmeier-oss@weidmueller.com Signed-off-by: Michal Simek <michal.simek@amd.com> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
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27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
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24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
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08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
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18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
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06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
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04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
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04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
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06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
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18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
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17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
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06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
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28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
e9e73d78 |
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17-Aug-2022 |
Michael Walle <michael@walle.cc> |
timer: add orion-timer support Add timer support for Kirkwood and MVEBU devices. Cc: Pali Rohár <pali@kernel.org> Signed-off-by: Michael Walle <michael@walle.cc> Acked-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de> |
#
c316ee67 |
|
27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
|
24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
|
08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
|
18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
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12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
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25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
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27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
c316ee67 |
|
27-Jun-2022 |
Tom Rini <trini@konsulko.com> |
Merge tag 'xilinx-for-v2022.10' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2022.10 cpu: - Add driver for microblaze cpu net: - Add support for DM_ETH_PHY to AXI emac and emaclite xilinx: - Switch platforms to DM_ETH_PHY - DT chagnes in ZynqMP and Zynq - Enable support for SquashFS zynqmp: - Add support for KR260 boards - Move BSS from address 0 - Move platform identification from board code to soc driver - Improve zynqmp_psu_init_minimize versal: - Enable loading app at EL1 serial: - Setup default address and clock rates for DEBUG uarts pinctrl: - Add support for tri state and output enable properties relocate-rela: - Clean relocate-rela implementation for ARM64 - Add support for Microblaze microblaze: - Add support for runtime relocation - Rework cache handling (wiring, Kconfig) based on cpuinfo - Remove interrupt support timer: - Extract axi timer driver from Microblaze to generic location
|
#
a36d8672 |
|
24-Jun-2022 |
Michal Simek <michal.simek@amd.com> |
microblaze: Convert axi timer to DM driver Move axi timer driver from Microblaze to generic location. Origin implementation was irq based with counting down timer. CONFIG_TIMER drivers are designed differently that timer is free running up timer with automatic reload without any interrupt. Information about clock rates are find out in timer_pre_probe() that's why there is no need to get any additional information from DT in the driver itself (only register offset). Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Ovidiu Panait <ovidiu.panait@windriver.com> Link: https://lore.kernel.org/r/6c12fc86bbc1f17d05c25018862e7b7b03346b36.1654684731.git.michal.simek@amd.com |
#
b25913b4 |
|
08-Jun-2022 |
Nick Hawkins <nick.hawkins@hpe.com> |
timer: gxp: Add HPE GXP timer support Add support for the HPE GXP SOC timer. The GXP supports several different kinds of timers but for the purpose of this driver there is only support for the General Timer. The timer has a 1us resolution and is 56 bits. Signed-off-by: Nick Hawkins <nick.hawkins@hpe.com> |
#
b789e4f2 |
|
18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
b789e4f2 |
|
18-Apr-2022 |
Jim Liu <jim.t90615@gmail.com> |
timer: npcm: Add NPCM timer support Add Nuvoton BMC NPCM7xx/NPCM8xx timer driver. Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Signed-off-by: Stanley Chu <yschu@nuvoton.com> |
#
632422d4 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
|
04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
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13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
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22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
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08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
632422d4 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_pit: introduce CONFIG_SPL_ATMEL_PIT_TIMER This commit allows the ATMEL_PIT_TIMER driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 0.3 KBytes. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
e135d2c2 |
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04-Apr-2022 |
Eugen Hristev <eugen.hristev@microchip.com> |
timers: atmel_tcb: introduce CONFIG_SPL_ATMEL_TCB This commit allows the ATMEL_TCB driver to be unselected in SPL and be selected in u-boot proper. The SPL can use a different timer. By having a separate Kconfig for ATMEL_TCB in SPL, the size of the SPL decreases by 1 KByte. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
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31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
11232139 |
|
06-Apr-2022 |
Tom Rini <trini@konsulko.com> |
nds32: Remove the architecture As removal of nds32 has been ack'd for the Linux kernel, remove support here as well. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Rick Chen <rick@andestech.com> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@amd.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
70fb1ae9 |
|
31-Mar-2022 |
Clément Léger <clement.leger@bootlin.com> |
timer: atmel_tcb_timer: add atmel_tcb driver Add a driver for the timer counter block that can be found on sama5d2. This driver will be used when booting under OP-TEE since the pit timer which is part of the SYSC is secured. Channel 1 & 2 are configured to be chained together which allows to have a 64bits counter. Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Signed-off-by: Clément Léger <clement.leger@bootlin.com> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marex@denx.de> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
f8c8573b |
|
12-May-2021 |
Giulio Benetti <giulio.benetti@benettiengineering.com> |
timer: imx-gpt: Add timer support for i.MX SoCs family This timer driver uses GPT Timer (General Purpose Timer) available on a lot of i.MX SoCs family. This driver deals with both 24Mhz oscillator as well as peripheral clock. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> [Giulio: added the driver's stub and handled peripheral clock prescaler setting making driver to work correctly] Signed-off-by: Jesse Taube <mr.bossman075@gmail.com> [Jesse: added init, setting prescaler for 24Mhz support and enabling timer] |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
a6d7e8c9 |
|
11-May-2021 |
Bin Meng <bmeng.cn@gmail.com> |
riscv: Split SiFive CLINT support between SPL and U-Boot proper At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to control the enabling of SiFive CLINT support in both SPL (M-mode) and U-Boot proper (S-mode). So for a typical SPL config that the SiFive CLINT driver is enabled in both SPL and U-Boot proper, that means the S-mode U-Boot tries to access the memory-mapped CLINT registers directly, instead of the normal 'rdtime' instruction. This was not a problem before, as the hardware does not forbid the access from S-mode. However this becomes an issue now with OpenSBI commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain") that the SiFive CLINT register space is protected by PMP for M-mode access only. U-Boot proper does not boot any more with the latest OpenSBI, that access exceptions are fired forever from U-Boot when trying to read the timer value via the SiFive CLINT driver in U-Boot. To solve this, we need to split current SiFive CLINT support between SPL and U-Boot proper, using 2 separate Kconfig options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@foss.st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@foss.st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
47d7e3b5 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move timer portions of SiFive CLINT to drivers/timer Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
7dbebebb |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
timer: Add _TIMER suffix to Andes PLMT Kconfig This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
79b135f1 |
|
25-Oct-2020 |
Sean Anderson <seanga2@gmail.com> |
riscv: Move Andes PLMT driver to drivers/timer This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com> |
#
ed1b7266 |
|
07-Sep-2020 |
Claudiu Beznea <claudiu.beznea@microchip.com> |
timer: mchp-pit64b: add support for pit64b Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
057b6139 |
|
04-Jan-2020 |
Stephan Gerhold <stephan@gerhold.net> |
timer: Add driver for Nomadik Multi Timer Unit (MTU) The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
4d0732bf |
|
04-May-2019 |
Marek Vasut <marek.vasut+renesas@gmail.com> |
timer: renesas: Add RZ/A1 R7S72100 OSTM timer driver Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
#
60262cd0 |
|
12-Dec-2018 |
Bin Meng <bmeng.cn@gmail.com> |
timer: Add generic driver for RISC-V privileged architecture defined timer RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org> |
#
d3c3606c |
|
14-Nov-2018 |
Ryder Lee <ryder.lee@mediatek.com> |
timer: MediaTek: add timer driver for MediaTek SoCs This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc> |
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com> |
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> |
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com> |
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com> |
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> |
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com> |
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org> |
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> |
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> |
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> |
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> |
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> |
#
2c21749d |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Add MPC83xx timer driver Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
|
#
d259f975 |
|
06-Aug-2018 |
Mario Six <mario.six@gdsys.cc> |
timer: Sort Makefile entries Makefile entries should be sorted. Signed-off-by: Mario Six <mario.six@gdsys.cc>
|
#
66011a08 |
|
18-Aug-2018 |
Marek Vasut <marex@denx.de> |
timer: dw-apb: Add Designware APB timer driver Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
|
#
72c37d12 |
|
17-Apr-2018 |
Michal Simek <michal.simek@xilinx.com> |
timer: Add Cadence TTC timer counter support This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
|
#
83d290c5 |
|
06-May-2018 |
Tom Rini <trini@konsulko.com> |
SPDX: Convert all of our single license tags to Linux Kernel style When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
|
#
5120a083 |
|
07-Feb-2018 |
Patrice Chotard <patrice.chotard@st.com> |
timer: stm32: Add timer support for STM32 SoCs family This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
|
#
fa3e354b |
|
27-Nov-2017 |
Rick Chen <rickchen36@gmail.com> |
ae3xx: timer: Rename AE3XX to ATCPIT100 ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
47edaea4 |
|
15-Aug-2017 |
Wenyou.Yang@microchip.com <Wenyou.Yang@microchip.com> |
driver: timer: Add the Atmel PIT timer driver Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
|
#
1168d2dd |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
rockchip: timer: add device-model timer driver for RK3368 (and similar) This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
e9e5d9d2 |
|
28-Jul-2017 |
Philipp Tomsich <philipp.tomsich@theobroma-systems.com> |
dm: timer: normalise SPL and TPL support To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
b841b6e9 |
|
18-May-2017 |
rick <rick@andestech.com> |
nds32: Support AE3XX platform. Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
|
#
f5076f86 |
|
16-May-2017 |
rick <rick@andestech.com> |
nds32: Support AG101P timer DM. Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
|
#
20699e6b |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
ad9b5f77 |
|
21-Mar-2017 |
Vlad Zakharov <vzakhar@synopsys.com> |
drivers: timer: Introduce ARC timer driver This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
347cb2ed |
|
21-Feb-2017 |
Patrice Chotard <patrice.chotard@st.com> |
STiH410: Add STi timer driver Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
4697abea |
|
18-Jan-2017 |
maxims@google.com <maxims@google.com> |
aspeed: Add drivers common to all Aspeed SoCs Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
dadf3137 |
|
24-Dec-2015 |
Mugunthan V N <mugunthanvnm@ti.com> |
drivers: timer: omap_timer: add timer driver for omap devices based on dm Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
|
#
7030f27e |
|
13-Nov-2015 |
Bin Meng <bmeng.cn@gmail.com> |
x86: tsc: Move tsc_timer.c to drivers/timer To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
|
#
9961a0b6 |
|
30-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
sandbox: add a sandbox timer and basic test Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
|
#
a54915d8 |
|
22-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
nios2: convert altera timer to driver model Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
|
#
c8a7ba9e |
|
08-Oct-2015 |
Thomas Chou <thomas@wytron.com.tw> |
dm: implement a Timer uclass Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
|