Searched refs:dsmpd (Results 1 - 8 of 8) sorted by relevance
| /u-boot/drivers/clk/starfive/ |
| H A D | clk-jh7110-pll.c | 59 u32 dsmpd; member in struct:starfive_pllx_offset
139 .dsmpd = 0x18,
156 .dsmpd = 0x24,
173 .dsmpd = 0x2c,
229 PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1);
248 u32 dacpd, dsmpd; local
254 dsmpd = getbits_le32((ulong)pll->base + pll->offset->dsmpd,
266 * Both dacpd and dsmpd should be set as 1 while integer multiple mode.
280 * Both dacpd and dsmpd shoul
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| /u-boot/arch/arm/include/asm/arch-rockchip/ |
| H A D | clock.h | 68 .dsmpd = _dsmpd, \
92 unsigned int dsmpd; member in struct:rockchip_pll_rate_table
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| H A D | cru_rv1126.h | 143 unsigned int dsmpd; member in struct:pll_rate_table
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| H A D | cru_px30.h | 106 unsigned int dsmpd; member in struct:pll_rate_table
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| H A D | cru_rk3568.h | 120 unsigned int dsmpd; member in struct:pll_rate_table
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| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 127 rate_table->dsmpd = 1;
164 rate_table->dsmpd = 0;
306 debug("%s: rate settings for %lu postdiv2: %d, dsmpd: %d, frac: %d\n",
307 __func__, rate->rate, rate->postdiv2, rate->dsmpd, rate->frac);
331 if (!rate->dsmpd) {
334 rate->dsmpd << RK3036_PLLCON1_DSMPD_SHIFT);
363 u32 refdiv, fbdiv, postdiv1, postdiv2, dsmpd, frac; local
386 dsmpd = (con & RK3036_PLLCON1_DSMPD_MASK) >>
392 if (dsmpd == 0) {
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| H A D | clk_px30.c | 43 .dsmpd = _dsmpd, \
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| /u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 308 u32 dsmpd = 1; local
341 dsmpd = 0;
352 writel(DSMPD(dsmpd) | POSTDIV2(postdiv2) | REFDIV(refdiv),
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