Searched refs:dpll (Results 1 - 10 of 10) sorted by relevance

/u-boot/arch/arm/mach-uniphier/clk/
H A DMakefile5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
14 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += pll-ld4.o dpll-tail.o
15 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-pro4.o pll-pro4.o dpll-tail.o
16 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += pll-ld4.o dpll-tail.o
/u-boot/drivers/clk/ti/
H A DMakefile8 obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
/u-boot/arch/arm/lib/
H A Dasm-offsets.c36 * - struct dpll
83 DEFINE(PLL_DP_CTL, offsetof(struct dpll, dp_ctl));
84 DEFINE(PLL_DP_CONFIG, offsetof(struct dpll, dp_config));
85 DEFINE(PLL_DP_OP, offsetof(struct dpll, dp_op));
86 DEFINE(PLL_DP_MFD, offsetof(struct dpll, dp_mfd));
87 DEFINE(PLL_DP_MFN, offsetof(struct dpll, dp_mfn));
88 DEFINE(PLL_DP_HFS_OP, offsetof(struct dpll, dp_hfs_op));
89 DEFINE(PLL_DP_HFS_MFD, offsetof(struct dpll, dp_hfs_mfd));
90 DEFINE(PLL_DP_HFS_MFN, offsetof(struct dpll, dp_hfs_mfn));
/u-boot/drivers/clk/
H A Dclk_zynqmp.c118 apll, dpll, vpll, enumerator in enum:zynqmp_clk
154 "iopll", "rpll", "apll", "dpll",
182 {apll, 0xff, dpll, vpll}, /* acpu */
183 {dpll, vpll, 0xff, 0xff}, /* ddr_ref */
186 {iopll, 0xff, rpll, dpll}, /* peripheral */
187 {apll, 0xff, iopll_to_fpd, dpll}, /* wdt */
188 {iopll_to_fpd, 0xff, dpll, apll}, /* dbg_fpd */
190 {iopll_to_fpd, 0xff, apll, dpll}, /* sata_ref */
191 {iopll_to_fpd, 0xff, rpll_to_fpd, dpll},/* pcie_ref */
192 {iopll_to_fpd, 0xff, vpll, dpll}, /* gpu_re
[all...]
/u-boot/drivers/clk/rockchip/
H A Dclk_rk3368.c137 u32 apllb, aplll, dpll, cpll, gpll; local
152 dpll = rkclk_pll_get_rate(cru, DPLL);
156 debug("%s apllb(%d) apll(%d) dpll(%d) cpll(%d) gpll(%d)\n",
157 __func__, apllb, aplll, dpll, cpll, gpll);
H A Dclk_rv1108.c636 unsigned int apll, dpll, gpll; local
655 dpll = rkclk_pll_get_rate(cru, CLK_DDR);
661 printf("APLL: %d DPLL:%d GPLL:%d\n", apll, dpll, gpll);
/u-boot/arch/arm/include/asm/arch-aspeed/
H A Dscu_ast2600.h186 uint32_t dpll; /* 0x260 */ member in struct:ast2600_scu
/u-boot/arch/arm/mach-omap2/
H A Dclocks-common.c60 /* SYS_CLKSEL - 1 to match the dpll param array indices */
214 u8 lock, char *dpll)
235 "N= %d" , dpll, params->m, params->n,
240 "nominal opp values", dpll);
308 * Lock MPU dpll
356 * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction
371 /* Now setup the dpll with the regular function */
384 /* CORE dpll */
405 /* lock PER dpll */
411 /* MPU dpll */
213 do_setup_dpll(u32 const base, const struct dpll_params *params, u8 lock, char *dpll) argument
[all...]
/u-boot/arch/arm/include/asm/arch-mx5/
H A Dimx-regs.h317 struct dpll { struct
/u-boot/drivers/clk/aspeed/
H A Dclk_ast2600.c152 pll_reg.w = readl(&scu->dpll);
524 addr = (uint32_t)(&scu->dpll);
1118 { ASPEED_CLK_DPLL, "dpll" },

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