Searched refs:dm_pci_clrset_config8 (Results 1 - 7 of 7) sorted by relevance

/u-boot/arch/x86/cpu/intel_common/
H A Dlpss.c43 dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state);
H A Dp2sb.c128 dm_pci_clrset_config8(dev, PCH_P2SB_E0 + 1, HIDE_BIT,
/u-boot/drivers/sound/
H A Divybridge_sound.c67 dm_pci_clrset_config8(dev, 0x43, 0, 1 << 6);
82 dm_pci_clrset_config8(dev, 0x40, 0, 1);
83 dm_pci_clrset_config8(dev, 0x4d, 1 << 7, 0); /* Docking not supported */
96 dm_pci_clrset_config8(dev, 0x43, 7, BIT(2) | BIT(0));
/u-boot/board/imgtec/malta/
H A Dmalta.c222 dm_pci_clrset_config8(dev, PCI_CFG_PIIX4_SERIRQC, 0,
/u-boot/arch/x86/cpu/broadwell/
H A Dpch.c90 dm_pci_clrset_config8(dev, GEN_PMCON_3, 3 << 4 | 1 << 10,
100 dm_pci_clrset_config8(dev, GEN_PMCON_2, 0, 1 << 7);
109 dm_pci_clrset_config8(dev, SERIRQ_CNTL, 0, 1 << 7 | 1 << 6);
560 dm_pci_clrset_config8(hda, 0x43, 0, 0x6f);
563 dm_pci_clrset_config8(hda, 0x42, 0, 1 << 7 | 1 << 6);
/u-boot/include/
H A Dpci.h1107 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
/u-boot/drivers/pci/
H A Dpci-uclass.c484 int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set) function

Completed in 133 milliseconds