Searched refs:div2 (Results 1 - 10 of 10) sorted by relevance
/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
H A D | clock.h | 30 unsigned int div2; member in struct:s5pc100_clock 66 unsigned int div2; member in struct:s5pc110_clock
|
/u-boot/drivers/clk/imx/ |
H A D | clk-composite-8m.c | 62 int div1, div2; local 70 for (div2 = 1; div2 <= PCG_DIV_MAX; div2++) { 71 int new_error = ((parent_rate / div1) / div2) - rate; 75 *postdiv = div2;
|
/u-boot/arch/arm/mach-sunxi/ |
H A D | clock_sun8i_a83t.c | 110 unsigned int div1 = 0, div2 = 0; local 112 /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */ 115 div2 << CCM_PLL5_DIV2_SHIFT | 131 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> local 133 return 24000000 * n / div1 / div2;
|
H A D | clock_sun50i_h6.c | 143 int div2 = ((rval & CCM_PLL6_CTRL_DIV2_MASK) >> local 160 return 24000000U * n / m / div1 / div2;
|
/u-boot/arch/arm/mach-keystone/include/mach/ |
H A D | clock_defs.h | 25 u32 div2; /* 1c */ member in struct:pllctl_regs
|
/u-boot/arch/arm/mach-imx/imx9/ |
H A D | clock.c | 110 bool div2, bool fracpll) 122 (div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT_DIV2)) || 123 (!div2 && !(dfs_ctrl & PLL_DFS_CTRL_CLKOUT))) 137 if (div2) 109 decode_pll_pfd(struct ana_pll_reg *reg, struct ana_pll_dfs *dfs_reg, bool div2, bool fracpll) argument
|
/u-boot/board/xilinx/zynqmp/zynqmp-smk-k24-revA/ |
H A D | psu_init_gpl.c | 9 static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, argument 17 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
|
/u-boot/board/xilinx/zynqmp/zynqmp-sm-k24-revA/ |
H A D | psu_init_gpl.c | 9 static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, argument 17 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
|
/u-boot/board/xilinx/zynqmp/zynqmp-e-a2197-00-revA/ |
H A D | psu_init_gpl.c | 932 static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, argument 940 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
|
/u-boot/board/xilinx/zynqmp/zynqmp-e-a2197-00-revB/ |
H A D | psu_init_gpl.c | 932 static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, argument 940 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16);
|
Completed in 142 milliseconds