1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (c) Copyright 2015 Xilinx, Inc. All rights reserved. 4 */ 5 6#include <asm/arch/psu_init_gpl.h> 7#include <xil_io.h> 8 9static int serdes_rst_seq(u32 pllsel, u32 lane3_protocol, u32 lane3_rate, 10 u32 lane2_protocol, u32 lane2_rate, 11 u32 lane1_protocol, u32 lane1_rate, 12 u32 lane0_protocol, u32 lane0_rate) 13{ 14 Xil_Out32(0xFD410098, 0x00000000); 15 Xil_Out32(0xFD401010, 0x00000040); 16 Xil_Out32(0xFD405010, 0x00000040); 17 Xil_Out32(0xFD409010, 0x00000040); 18 Xil_Out32(0xFD40D010, 0x00000040); 19 Xil_Out32(0xFD402084, 0x00000080); 20 Xil_Out32(0xFD406084, 0x00000080); 21 Xil_Out32(0xFD40A084, 0x00000080); 22 Xil_Out32(0xFD40E084, 0x00000080); 23 Xil_Out32(0xFD410098, 0x00000004); 24 mask_delay(50); 25 if (lane0_rate == 1) 26 Xil_Out32(0xFD410098, 0x0000000E); 27 Xil_Out32(0xFD410098, 0x00000006); 28 if (lane0_rate == 1) { 29 Xil_Out32(0xFD40000C, 0x00000004); 30 Xil_Out32(0xFD40400C, 0x00000004); 31 Xil_Out32(0xFD40800C, 0x00000004); 32 Xil_Out32(0xFD40C00C, 0x00000004); 33 Xil_Out32(0xFD410098, 0x00000007); 34 mask_delay(400); 35 Xil_Out32(0xFD40000C, 0x0000000C); 36 Xil_Out32(0xFD40400C, 0x0000000C); 37 Xil_Out32(0xFD40800C, 0x0000000C); 38 Xil_Out32(0xFD40C00C, 0x0000000C); 39 mask_delay(15); 40 Xil_Out32(0xFD410098, 0x0000000F); 41 mask_delay(100); 42 } 43 if (pllsel == 0) 44 mask_poll(0xFD4023E4, 0x00000010U); 45 if (pllsel == 1) 46 mask_poll(0xFD4063E4, 0x00000010U); 47 if (pllsel == 2) 48 mask_poll(0xFD40A3E4, 0x00000010U); 49 if (pllsel == 3) 50 mask_poll(0xFD40E3E4, 0x00000010U); 51 mask_delay(50); 52 Xil_Out32(0xFD401010, 0x000000C0); 53 Xil_Out32(0xFD405010, 0x000000C0); 54 Xil_Out32(0xFD409010, 0x000000C0); 55 Xil_Out32(0xFD40D010, 0x000000C0); 56 Xil_Out32(0xFD401010, 0x00000080); 57 Xil_Out32(0xFD405010, 0x00000080); 58 Xil_Out32(0xFD409010, 0x00000080); 59 Xil_Out32(0xFD40D010, 0x00000080); 60 61 Xil_Out32(0xFD402084, 0x000000C0); 62 Xil_Out32(0xFD406084, 0x000000C0); 63 Xil_Out32(0xFD40A084, 0x000000C0); 64 Xil_Out32(0xFD40E084, 0x000000C0); 65 mask_delay(50); 66 Xil_Out32(0xFD402084, 0x00000080); 67 Xil_Out32(0xFD406084, 0x00000080); 68 Xil_Out32(0xFD40A084, 0x00000080); 69 Xil_Out32(0xFD40E084, 0x00000080); 70 mask_delay(50); 71 Xil_Out32(0xFD401010, 0x00000000); 72 Xil_Out32(0xFD405010, 0x00000000); 73 Xil_Out32(0xFD409010, 0x00000000); 74 Xil_Out32(0xFD40D010, 0x00000000); 75 Xil_Out32(0xFD402084, 0x00000000); 76 Xil_Out32(0xFD406084, 0x00000000); 77 Xil_Out32(0xFD40A084, 0x00000000); 78 Xil_Out32(0xFD40E084, 0x00000000); 79 mask_delay(500); 80 return 1; 81} 82 83static int serdes_bist_static_settings(u32 lane_active) 84{ 85 if (lane_active == 0) { 86 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); 87 Xil_Out32(0xFD403068, 0x1); 88 Xil_Out32(0xFD40306C, 0x1); 89 Xil_Out32(0xFD4010AC, 0x0020); 90 Xil_Out32(0xFD403008, 0x0); 91 Xil_Out32(0xFD40300C, 0xF4); 92 Xil_Out32(0xFD403010, 0x0); 93 Xil_Out32(0xFD403014, 0x0); 94 Xil_Out32(0xFD403018, 0x00); 95 Xil_Out32(0xFD40301C, 0xFB); 96 Xil_Out32(0xFD403020, 0xFF); 97 Xil_Out32(0xFD403024, 0x0); 98 Xil_Out32(0xFD403028, 0x00); 99 Xil_Out32(0xFD40302C, 0x00); 100 Xil_Out32(0xFD403030, 0x4A); 101 Xil_Out32(0xFD403034, 0x4A); 102 Xil_Out32(0xFD403038, 0x4A); 103 Xil_Out32(0xFD40303C, 0x4A); 104 Xil_Out32(0xFD403040, 0x0); 105 Xil_Out32(0xFD403044, 0x14); 106 Xil_Out32(0xFD403048, 0x02); 107 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) & 0xFFFFFF1F)); 108 } 109 if (lane_active == 1) { 110 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); 111 Xil_Out32(0xFD407068, 0x1); 112 Xil_Out32(0xFD40706C, 0x1); 113 Xil_Out32(0xFD4050AC, 0x0020); 114 Xil_Out32(0xFD407008, 0x0); 115 Xil_Out32(0xFD40700C, 0xF4); 116 Xil_Out32(0xFD407010, 0x0); 117 Xil_Out32(0xFD407014, 0x0); 118 Xil_Out32(0xFD407018, 0x00); 119 Xil_Out32(0xFD40701C, 0xFB); 120 Xil_Out32(0xFD407020, 0xFF); 121 Xil_Out32(0xFD407024, 0x0); 122 Xil_Out32(0xFD407028, 0x00); 123 Xil_Out32(0xFD40702C, 0x00); 124 Xil_Out32(0xFD407030, 0x4A); 125 Xil_Out32(0xFD407034, 0x4A); 126 Xil_Out32(0xFD407038, 0x4A); 127 Xil_Out32(0xFD40703C, 0x4A); 128 Xil_Out32(0xFD407040, 0x0); 129 Xil_Out32(0xFD407044, 0x14); 130 Xil_Out32(0xFD407048, 0x02); 131 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) & 0xFFFFFF1F)); 132 } 133 134 if (lane_active == 2) { 135 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); 136 Xil_Out32(0xFD40B068, 0x1); 137 Xil_Out32(0xFD40B06C, 0x1); 138 Xil_Out32(0xFD4090AC, 0x0020); 139 Xil_Out32(0xFD40B008, 0x0); 140 Xil_Out32(0xFD40B00C, 0xF4); 141 Xil_Out32(0xFD40B010, 0x0); 142 Xil_Out32(0xFD40B014, 0x0); 143 Xil_Out32(0xFD40B018, 0x00); 144 Xil_Out32(0xFD40B01C, 0xFB); 145 Xil_Out32(0xFD40B020, 0xFF); 146 Xil_Out32(0xFD40B024, 0x0); 147 Xil_Out32(0xFD40B028, 0x00); 148 Xil_Out32(0xFD40B02C, 0x00); 149 Xil_Out32(0xFD40B030, 0x4A); 150 Xil_Out32(0xFD40B034, 0x4A); 151 Xil_Out32(0xFD40B038, 0x4A); 152 Xil_Out32(0xFD40B03C, 0x4A); 153 Xil_Out32(0xFD40B040, 0x0); 154 Xil_Out32(0xFD40B044, 0x14); 155 Xil_Out32(0xFD40B048, 0x02); 156 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) & 0xFFFFFF1F)); 157 } 158 159 if (lane_active == 3) { 160 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); 161 Xil_Out32(0xFD40F068, 0x1); 162 Xil_Out32(0xFD40F06C, 0x1); 163 Xil_Out32(0xFD40D0AC, 0x0020); 164 Xil_Out32(0xFD40F008, 0x0); 165 Xil_Out32(0xFD40F00C, 0xF4); 166 Xil_Out32(0xFD40F010, 0x0); 167 Xil_Out32(0xFD40F014, 0x0); 168 Xil_Out32(0xFD40F018, 0x00); 169 Xil_Out32(0xFD40F01C, 0xFB); 170 Xil_Out32(0xFD40F020, 0xFF); 171 Xil_Out32(0xFD40F024, 0x0); 172 Xil_Out32(0xFD40F028, 0x00); 173 Xil_Out32(0xFD40F02C, 0x00); 174 Xil_Out32(0xFD40F030, 0x4A); 175 Xil_Out32(0xFD40F034, 0x4A); 176 Xil_Out32(0xFD40F038, 0x4A); 177 Xil_Out32(0xFD40F03C, 0x4A); 178 Xil_Out32(0xFD40F040, 0x0); 179 Xil_Out32(0xFD40F044, 0x14); 180 Xil_Out32(0xFD40F048, 0x02); 181 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) & 0xFFFFFF1F)); 182 } 183 return 1; 184} 185 186static int serdes_bist_run(u32 lane_active) 187{ 188 if (lane_active == 0) { 189 psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); 190 psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); 191 psu_mask_write(0xFD410038, 0x00000007U, 0x00000001U); 192 Xil_Out32(0xFD4010AC, 0x0020); 193 Xil_Out32(0xFD403004, (Xil_In32(0xFD403004) | 0x1)); 194 } 195 if (lane_active == 1) { 196 psu_mask_write(0xFD410044, 0x0000000CU, 0x00000000U); 197 psu_mask_write(0xFD410040, 0x0000000CU, 0x00000000U); 198 psu_mask_write(0xFD410038, 0x00000070U, 0x00000010U); 199 Xil_Out32(0xFD4050AC, 0x0020); 200 Xil_Out32(0xFD407004, (Xil_In32(0xFD407004) | 0x1)); 201 } 202 if (lane_active == 2) { 203 psu_mask_write(0xFD410044, 0x00000030U, 0x00000000U); 204 psu_mask_write(0xFD410040, 0x00000030U, 0x00000000U); 205 psu_mask_write(0xFD41003C, 0x00000007U, 0x00000001U); 206 Xil_Out32(0xFD4090AC, 0x0020); 207 Xil_Out32(0xFD40B004, (Xil_In32(0xFD40B004) | 0x1)); 208 } 209 if (lane_active == 3) { 210 psu_mask_write(0xFD410040, 0x000000C0U, 0x00000000U); 211 psu_mask_write(0xFD410044, 0x000000C0U, 0x00000000U); 212 psu_mask_write(0xFD41003C, 0x00000070U, 0x00000010U); 213 Xil_Out32(0xFD40D0AC, 0x0020); 214 Xil_Out32(0xFD40F004, (Xil_In32(0xFD40F004) | 0x1)); 215 } 216 mask_delay(100); 217 return 1; 218} 219 220static int serdes_bist_result(u32 lane_active) 221{ 222 u32 pkt_cnt_l0, pkt_cnt_h0, err_cnt_l0, err_cnt_h0; 223 224 if (lane_active == 0) { 225 pkt_cnt_l0 = Xil_In32(0xFD40304C); 226 pkt_cnt_h0 = Xil_In32(0xFD403050); 227 err_cnt_l0 = Xil_In32(0xFD403054); 228 err_cnt_h0 = Xil_In32(0xFD403058); 229 } 230 if (lane_active == 1) { 231 pkt_cnt_l0 = Xil_In32(0xFD40704C); 232 pkt_cnt_h0 = Xil_In32(0xFD407050); 233 err_cnt_l0 = Xil_In32(0xFD407054); 234 err_cnt_h0 = Xil_In32(0xFD407058); 235 } 236 if (lane_active == 2) { 237 pkt_cnt_l0 = Xil_In32(0xFD40B04C); 238 pkt_cnt_h0 = Xil_In32(0xFD40B050); 239 err_cnt_l0 = Xil_In32(0xFD40B054); 240 err_cnt_h0 = Xil_In32(0xFD40B058); 241 } 242 if (lane_active == 3) { 243 pkt_cnt_l0 = Xil_In32(0xFD40F04C); 244 pkt_cnt_h0 = Xil_In32(0xFD40F050); 245 err_cnt_l0 = Xil_In32(0xFD40F054); 246 err_cnt_h0 = Xil_In32(0xFD40F058); 247 } 248 if (lane_active == 0) 249 Xil_Out32(0xFD403004, 0x0); 250 if (lane_active == 1) 251 Xil_Out32(0xFD407004, 0x0); 252 if (lane_active == 2) 253 Xil_Out32(0xFD40B004, 0x0); 254 if (lane_active == 3) 255 Xil_Out32(0xFD40F004, 0x0); 256 if (err_cnt_l0 > 0 || err_cnt_h0 > 0 || 257 (pkt_cnt_l0 == 0 && pkt_cnt_h0 == 0)) 258 return 0; 259 return 1; 260} 261 262static int serdes_illcalib_pcie_gen1(u32 pllsel, u32 lane3_protocol, 263 u32 lane3_rate, u32 lane2_protocol, 264 u32 lane2_rate, u32 lane1_protocol, 265 u32 lane1_rate, u32 lane0_protocol, 266 u32 lane0_rate, u32 gen2_calib) 267{ 268 u64 tempbistresult; 269 u32 currbistresult[4]; 270 u32 prevbistresult[4]; 271 u32 itercount = 0; 272 u32 ill12_val[4], ill1_val[4]; 273 u32 loop = 0; 274 u32 iterresult[8]; 275 u32 meancount[4]; 276 u32 bistpasscount[4]; 277 u32 meancountalt[4]; 278 u32 meancountalt_bistpasscount[4]; 279 u32 lane0_active; 280 u32 lane1_active; 281 u32 lane2_active; 282 u32 lane3_active; 283 284 lane0_active = (lane0_protocol == 1); 285 lane1_active = (lane1_protocol == 1); 286 lane2_active = (lane2_protocol == 1); 287 lane3_active = (lane3_protocol == 1); 288 for (loop = 0; loop <= 3; loop++) { 289 iterresult[loop] = 0; 290 iterresult[loop + 4] = 0; 291 meancountalt[loop] = 0; 292 meancountalt_bistpasscount[loop] = 0; 293 meancount[loop] = 0; 294 prevbistresult[loop] = 0; 295 bistpasscount[loop] = 0; 296 } 297 itercount = 0; 298 if (lane0_active) 299 serdes_bist_static_settings(0); 300 if (lane1_active) 301 serdes_bist_static_settings(1); 302 if (lane2_active) 303 serdes_bist_static_settings(2); 304 if (lane3_active) 305 serdes_bist_static_settings(3); 306 do { 307 if (gen2_calib != 1) { 308 if (lane0_active == 1) 309 ill1_val[0] = ((0x04 + itercount * 8) % 0x100); 310 if (lane0_active == 1) 311 ill12_val[0] = 312 ((0x04 + itercount * 8) >= 313 0x100) ? 0x10 : 0x00; 314 if (lane1_active == 1) 315 ill1_val[1] = ((0x04 + itercount * 8) % 0x100); 316 if (lane1_active == 1) 317 ill12_val[1] = 318 ((0x04 + itercount * 8) >= 319 0x100) ? 0x10 : 0x00; 320 if (lane2_active == 1) 321 ill1_val[2] = ((0x04 + itercount * 8) % 0x100); 322 if (lane2_active == 1) 323 ill12_val[2] = 324 ((0x04 + itercount * 8) >= 325 0x100) ? 0x10 : 0x00; 326 if (lane3_active == 1) 327 ill1_val[3] = ((0x04 + itercount * 8) % 0x100); 328 if (lane3_active == 1) 329 ill12_val[3] = 330 ((0x04 + itercount * 8) >= 331 0x100) ? 0x10 : 0x00; 332 333 if (lane0_active == 1) 334 Xil_Out32(0xFD401924, ill1_val[0]); 335 if (lane0_active == 1) 336 psu_mask_write(0xFD401990, 0x000000F0U, 337 ill12_val[0]); 338 if (lane1_active == 1) 339 Xil_Out32(0xFD405924, ill1_val[1]); 340 if (lane1_active == 1) 341 psu_mask_write(0xFD405990, 0x000000F0U, 342 ill12_val[1]); 343 if (lane2_active == 1) 344 Xil_Out32(0xFD409924, ill1_val[2]); 345 if (lane2_active == 1) 346 psu_mask_write(0xFD409990, 0x000000F0U, 347 ill12_val[2]); 348 if (lane3_active == 1) 349 Xil_Out32(0xFD40D924, ill1_val[3]); 350 if (lane3_active == 1) 351 psu_mask_write(0xFD40D990, 0x000000F0U, 352 ill12_val[3]); 353 } 354 if (gen2_calib == 1) { 355 if (lane0_active == 1) 356 ill1_val[0] = ((0x104 + itercount * 8) % 0x100); 357 if (lane0_active == 1) 358 ill12_val[0] = 359 ((0x104 + itercount * 8) >= 360 0x200) ? 0x02 : 0x01; 361 if (lane1_active == 1) 362 ill1_val[1] = ((0x104 + itercount * 8) % 0x100); 363 if (lane1_active == 1) 364 ill12_val[1] = 365 ((0x104 + itercount * 8) >= 366 0x200) ? 0x02 : 0x01; 367 if (lane2_active == 1) 368 ill1_val[2] = ((0x104 + itercount * 8) % 0x100); 369 if (lane2_active == 1) 370 ill12_val[2] = 371 ((0x104 + itercount * 8) >= 372 0x200) ? 0x02 : 0x01; 373 if (lane3_active == 1) 374 ill1_val[3] = ((0x104 + itercount * 8) % 0x100); 375 if (lane3_active == 1) 376 ill12_val[3] = 377 ((0x104 + itercount * 8) >= 378 0x200) ? 0x02 : 0x01; 379 380 if (lane0_active == 1) 381 Xil_Out32(0xFD401928, ill1_val[0]); 382 if (lane0_active == 1) 383 psu_mask_write(0xFD401990, 0x0000000FU, 384 ill12_val[0]); 385 if (lane1_active == 1) 386 Xil_Out32(0xFD405928, ill1_val[1]); 387 if (lane1_active == 1) 388 psu_mask_write(0xFD405990, 0x0000000FU, 389 ill12_val[1]); 390 if (lane2_active == 1) 391 Xil_Out32(0xFD409928, ill1_val[2]); 392 if (lane2_active == 1) 393 psu_mask_write(0xFD409990, 0x0000000FU, 394 ill12_val[2]); 395 if (lane3_active == 1) 396 Xil_Out32(0xFD40D928, ill1_val[3]); 397 if (lane3_active == 1) 398 psu_mask_write(0xFD40D990, 0x0000000FU, 399 ill12_val[3]); 400 } 401 402 if (lane0_active == 1) 403 psu_mask_write(0xFD401018, 0x00000030U, 0x00000010U); 404 if (lane1_active == 1) 405 psu_mask_write(0xFD405018, 0x00000030U, 0x00000010U); 406 if (lane2_active == 1) 407 psu_mask_write(0xFD409018, 0x00000030U, 0x00000010U); 408 if (lane3_active == 1) 409 psu_mask_write(0xFD40D018, 0x00000030U, 0x00000010U); 410 if (lane0_active == 1) 411 currbistresult[0] = 0; 412 if (lane1_active == 1) 413 currbistresult[1] = 0; 414 if (lane2_active == 1) 415 currbistresult[2] = 0; 416 if (lane3_active == 1) 417 currbistresult[3] = 0; 418 serdes_rst_seq(pllsel, lane3_protocol, lane3_rate, 419 lane2_protocol, lane2_rate, lane1_protocol, 420 lane1_rate, lane0_protocol, lane0_rate); 421 if (lane3_active == 1) 422 serdes_bist_run(3); 423 if (lane2_active == 1) 424 serdes_bist_run(2); 425 if (lane1_active == 1) 426 serdes_bist_run(1); 427 if (lane0_active == 1) 428 serdes_bist_run(0); 429 tempbistresult = 0; 430 if (lane3_active == 1) 431 tempbistresult = tempbistresult | serdes_bist_result(3); 432 tempbistresult = tempbistresult << 1; 433 if (lane2_active == 1) 434 tempbistresult = tempbistresult | serdes_bist_result(2); 435 tempbistresult = tempbistresult << 1; 436 if (lane1_active == 1) 437 tempbistresult = tempbistresult | serdes_bist_result(1); 438 tempbistresult = tempbistresult << 1; 439 if (lane0_active == 1) 440 tempbistresult = tempbistresult | serdes_bist_result(0); 441 Xil_Out32(0xFD410098, 0x0); 442 Xil_Out32(0xFD410098, 0x2); 443 444 if (itercount < 32) { 445 iterresult[0] = 446 ((iterresult[0] << 1) | 447 ((tempbistresult & 0x1) == 0x1)); 448 iterresult[1] = 449 ((iterresult[1] << 1) | 450 ((tempbistresult & 0x2) == 0x2)); 451 iterresult[2] = 452 ((iterresult[2] << 1) | 453 ((tempbistresult & 0x4) == 0x4)); 454 iterresult[3] = 455 ((iterresult[3] << 1) | 456 ((tempbistresult & 0x8) == 0x8)); 457 } else { 458 iterresult[4] = 459 ((iterresult[4] << 1) | 460 ((tempbistresult & 0x1) == 0x1)); 461 iterresult[5] = 462 ((iterresult[5] << 1) | 463 ((tempbistresult & 0x2) == 0x2)); 464 iterresult[6] = 465 ((iterresult[6] << 1) | 466 ((tempbistresult & 0x4) == 0x4)); 467 iterresult[7] = 468 ((iterresult[7] << 1) | 469 ((tempbistresult & 0x8) == 0x8)); 470 } 471 currbistresult[0] = 472 currbistresult[0] | ((tempbistresult & 0x1) == 1); 473 currbistresult[1] = 474 currbistresult[1] | ((tempbistresult & 0x2) == 0x2); 475 currbistresult[2] = 476 currbistresult[2] | ((tempbistresult & 0x4) == 0x4); 477 currbistresult[3] = 478 currbistresult[3] | ((tempbistresult & 0x8) == 0x8); 479 480 for (loop = 0; loop <= 3; loop++) { 481 if (currbistresult[loop] == 1 && 482 prevbistresult[loop] == 1) 483 bistpasscount[loop] = bistpasscount[loop] + 1; 484 if (bistpasscount[loop] < 4 && 485 currbistresult[loop] == 0 && itercount > 2) { 486 if (meancountalt_bistpasscount[loop] < 487 bistpasscount[loop]) { 488 meancountalt_bistpasscount[loop] = 489 bistpasscount[loop]; 490 meancountalt[loop] = 491 ((itercount - 1) - 492 ((bistpasscount[loop] + 1) / 2)); 493 } 494 bistpasscount[loop] = 0; 495 } 496 if (meancount[loop] == 0 && bistpasscount[loop] >= 4 && 497 (currbistresult[loop] == 0 || itercount == 63) && 498 prevbistresult[loop] == 1) 499 meancount[loop] = 500 itercount - 1 - 501 ((bistpasscount[loop] + 1) / 2); 502 prevbistresult[loop] = currbistresult[loop]; 503 } 504 } while (++itercount < 64); 505 506 for (loop = 0; loop <= 3; loop++) { 507 if (lane0_active == 0 && loop == 0) 508 continue; 509 if (lane1_active == 0 && loop == 1) 510 continue; 511 if (lane2_active == 0 && loop == 2) 512 continue; 513 if (lane3_active == 0 && loop == 3) 514 continue; 515 516 if (meancount[loop] == 0) 517 meancount[loop] = meancountalt[loop]; 518 519 if (gen2_calib != 1) { 520 ill1_val[loop] = ((0x04 + meancount[loop] * 8) % 0x100); 521 ill12_val[loop] = 522 ((0x04 + meancount[loop] * 8) >= 523 0x100) ? 0x10 : 0x00; 524 } 525 if (gen2_calib == 1) { 526 ill1_val[loop] = 527 ((0x104 + meancount[loop] * 8) % 0x100); 528 ill12_val[loop] = 529 ((0x104 + meancount[loop] * 8) >= 530 0x200) ? 0x02 : 0x01; 531 } 532 } 533 if (gen2_calib != 1) { 534 if (lane0_active == 1) 535 Xil_Out32(0xFD401924, ill1_val[0]); 536 if (lane0_active == 1) 537 psu_mask_write(0xFD401990, 0x000000F0U, ill12_val[0]); 538 if (lane1_active == 1) 539 Xil_Out32(0xFD405924, ill1_val[1]); 540 if (lane1_active == 1) 541 psu_mask_write(0xFD405990, 0x000000F0U, ill12_val[1]); 542 if (lane2_active == 1) 543 Xil_Out32(0xFD409924, ill1_val[2]); 544 if (lane2_active == 1) 545 psu_mask_write(0xFD409990, 0x000000F0U, ill12_val[2]); 546 if (lane3_active == 1) 547 Xil_Out32(0xFD40D924, ill1_val[3]); 548 if (lane3_active == 1) 549 psu_mask_write(0xFD40D990, 0x000000F0U, ill12_val[3]); 550 } 551 if (gen2_calib == 1) { 552 if (lane0_active == 1) 553 Xil_Out32(0xFD401928, ill1_val[0]); 554 if (lane0_active == 1) 555 psu_mask_write(0xFD401990, 0x0000000FU, ill12_val[0]); 556 if (lane1_active == 1) 557 Xil_Out32(0xFD405928, ill1_val[1]); 558 if (lane1_active == 1) 559 psu_mask_write(0xFD405990, 0x0000000FU, ill12_val[1]); 560 if (lane2_active == 1) 561 Xil_Out32(0xFD409928, ill1_val[2]); 562 if (lane2_active == 1) 563 psu_mask_write(0xFD409990, 0x0000000FU, ill12_val[2]); 564 if (lane3_active == 1) 565 Xil_Out32(0xFD40D928, ill1_val[3]); 566 if (lane3_active == 1) 567 psu_mask_write(0xFD40D990, 0x0000000FU, ill12_val[3]); 568 } 569 570 if (lane0_active == 1) 571 psu_mask_write(0xFD401018, 0x00000030U, 0x00000000U); 572 if (lane1_active == 1) 573 psu_mask_write(0xFD405018, 0x00000030U, 0x00000000U); 574 if (lane2_active == 1) 575 psu_mask_write(0xFD409018, 0x00000030U, 0x00000000U); 576 if (lane3_active == 1) 577 psu_mask_write(0xFD40D018, 0x00000030U, 0x00000000U); 578 579 Xil_Out32(0xFD410098, 0); 580 if (lane0_active == 1) { 581 Xil_Out32(0xFD403004, 0); 582 Xil_Out32(0xFD403008, 0); 583 Xil_Out32(0xFD40300C, 0); 584 Xil_Out32(0xFD403010, 0); 585 Xil_Out32(0xFD403014, 0); 586 Xil_Out32(0xFD403018, 0); 587 Xil_Out32(0xFD40301C, 0); 588 Xil_Out32(0xFD403020, 0); 589 Xil_Out32(0xFD403024, 0); 590 Xil_Out32(0xFD403028, 0); 591 Xil_Out32(0xFD40302C, 0); 592 Xil_Out32(0xFD403030, 0); 593 Xil_Out32(0xFD403034, 0); 594 Xil_Out32(0xFD403038, 0); 595 Xil_Out32(0xFD40303C, 0); 596 Xil_Out32(0xFD403040, 0); 597 Xil_Out32(0xFD403044, 0); 598 Xil_Out32(0xFD403048, 0); 599 Xil_Out32(0xFD40304C, 0); 600 Xil_Out32(0xFD403050, 0); 601 Xil_Out32(0xFD403054, 0); 602 Xil_Out32(0xFD403058, 0); 603 Xil_Out32(0xFD403068, 1); 604 Xil_Out32(0xFD40306C, 0); 605 Xil_Out32(0xFD4010AC, 0); 606 psu_mask_write(0xFD410044, 0x00000003U, 0x00000001U); 607 psu_mask_write(0xFD410040, 0x00000003U, 0x00000001U); 608 psu_mask_write(0xFD410038, 0x00000007U, 0x00000000U); 609 } 610 if (lane1_active == 1) { 611 Xil_Out32(0xFD407004, 0); 612 Xil_Out32(0xFD407008, 0); 613 Xil_Out32(0xFD40700C, 0); 614 Xil_Out32(0xFD407010, 0); 615 Xil_Out32(0xFD407014, 0); 616 Xil_Out32(0xFD407018, 0); 617 Xil_Out32(0xFD40701C, 0); 618 Xil_Out32(0xFD407020, 0); 619 Xil_Out32(0xFD407024, 0); 620 Xil_Out32(0xFD407028, 0); 621 Xil_Out32(0xFD40702C, 0); 622 Xil_Out32(0xFD407030, 0); 623 Xil_Out32(0xFD407034, 0); 624 Xil_Out32(0xFD407038, 0); 625 Xil_Out32(0xFD40703C, 0); 626 Xil_Out32(0xFD407040, 0); 627 Xil_Out32(0xFD407044, 0); 628 Xil_Out32(0xFD407048, 0); 629 Xil_Out32(0xFD40704C, 0); 630 Xil_Out32(0xFD407050, 0); 631 Xil_Out32(0xFD407054, 0); 632 Xil_Out32(0xFD407058, 0); 633 Xil_Out32(0xFD407068, 1); 634 Xil_Out32(0xFD40706C, 0); 635 Xil_Out32(0xFD4050AC, 0); 636 psu_mask_write(0xFD410044, 0x0000000CU, 0x00000004U); 637 psu_mask_write(0xFD410040, 0x0000000CU, 0x00000004U); 638 psu_mask_write(0xFD410038, 0x00000070U, 0x00000000U); 639 } 640 if (lane2_active == 1) { 641 Xil_Out32(0xFD40B004, 0); 642 Xil_Out32(0xFD40B008, 0); 643 Xil_Out32(0xFD40B00C, 0); 644 Xil_Out32(0xFD40B010, 0); 645 Xil_Out32(0xFD40B014, 0); 646 Xil_Out32(0xFD40B018, 0); 647 Xil_Out32(0xFD40B01C, 0); 648 Xil_Out32(0xFD40B020, 0); 649 Xil_Out32(0xFD40B024, 0); 650 Xil_Out32(0xFD40B028, 0); 651 Xil_Out32(0xFD40B02C, 0); 652 Xil_Out32(0xFD40B030, 0); 653 Xil_Out32(0xFD40B034, 0); 654 Xil_Out32(0xFD40B038, 0); 655 Xil_Out32(0xFD40B03C, 0); 656 Xil_Out32(0xFD40B040, 0); 657 Xil_Out32(0xFD40B044, 0); 658 Xil_Out32(0xFD40B048, 0); 659 Xil_Out32(0xFD40B04C, 0); 660 Xil_Out32(0xFD40B050, 0); 661 Xil_Out32(0xFD40B054, 0); 662 Xil_Out32(0xFD40B058, 0); 663 Xil_Out32(0xFD40B068, 1); 664 Xil_Out32(0xFD40B06C, 0); 665 Xil_Out32(0xFD4090AC, 0); 666 psu_mask_write(0xFD410044, 0x00000030U, 0x00000010U); 667 psu_mask_write(0xFD410040, 0x00000030U, 0x00000010U); 668 psu_mask_write(0xFD41003C, 0x00000007U, 0x00000000U); 669 } 670 if (lane3_active == 1) { 671 Xil_Out32(0xFD40F004, 0); 672 Xil_Out32(0xFD40F008, 0); 673 Xil_Out32(0xFD40F00C, 0); 674 Xil_Out32(0xFD40F010, 0); 675 Xil_Out32(0xFD40F014, 0); 676 Xil_Out32(0xFD40F018, 0); 677 Xil_Out32(0xFD40F01C, 0); 678 Xil_Out32(0xFD40F020, 0); 679 Xil_Out32(0xFD40F024, 0); 680 Xil_Out32(0xFD40F028, 0); 681 Xil_Out32(0xFD40F02C, 0); 682 Xil_Out32(0xFD40F030, 0); 683 Xil_Out32(0xFD40F034, 0); 684 Xil_Out32(0xFD40F038, 0); 685 Xil_Out32(0xFD40F03C, 0); 686 Xil_Out32(0xFD40F040, 0); 687 Xil_Out32(0xFD40F044, 0); 688 Xil_Out32(0xFD40F048, 0); 689 Xil_Out32(0xFD40F04C, 0); 690 Xil_Out32(0xFD40F050, 0); 691 Xil_Out32(0xFD40F054, 0); 692 Xil_Out32(0xFD40F058, 0); 693 Xil_Out32(0xFD40F068, 1); 694 Xil_Out32(0xFD40F06C, 0); 695 Xil_Out32(0xFD40D0AC, 0); 696 psu_mask_write(0xFD410044, 0x000000C0U, 0x00000040U); 697 psu_mask_write(0xFD410040, 0x000000C0U, 0x00000040U); 698 psu_mask_write(0xFD41003C, 0x00000070U, 0x00000000U); 699 } 700 return 1; 701} 702 703static int serdes_illcalib(u32 lane3_protocol, u32 lane3_rate, 704 u32 lane2_protocol, u32 lane2_rate, 705 u32 lane1_protocol, u32 lane1_rate, 706 u32 lane0_protocol, u32 lane0_rate) 707{ 708 unsigned int rdata = 0; 709 unsigned int sata_gen2 = 1; 710 unsigned int temp_ill12 = 0; 711 unsigned int temp_PLL_REF_SEL_OFFSET; 712 unsigned int temp_TM_IQ_ILL1; 713 unsigned int temp_TM_E_ILL1; 714 unsigned int temp_tx_dig_tm_61; 715 unsigned int temp_tm_dig_6; 716 unsigned int temp_pll_fbdiv_frac_3_msb_offset; 717 718 if (lane0_protocol == 2 || lane0_protocol == 1) { 719 Xil_Out32(0xFD401910, 0xF3); 720 Xil_Out32(0xFD40193C, 0xF3); 721 Xil_Out32(0xFD401914, 0xF3); 722 Xil_Out32(0xFD401940, 0xF3); 723 } 724 if (lane1_protocol == 2 || lane1_protocol == 1) { 725 Xil_Out32(0xFD405910, 0xF3); 726 Xil_Out32(0xFD40593C, 0xF3); 727 Xil_Out32(0xFD405914, 0xF3); 728 Xil_Out32(0xFD405940, 0xF3); 729 } 730 if (lane2_protocol == 2 || lane2_protocol == 1) { 731 Xil_Out32(0xFD409910, 0xF3); 732 Xil_Out32(0xFD40993C, 0xF3); 733 Xil_Out32(0xFD409914, 0xF3); 734 Xil_Out32(0xFD409940, 0xF3); 735 } 736 if (lane3_protocol == 2 || lane3_protocol == 1) { 737 Xil_Out32(0xFD40D910, 0xF3); 738 Xil_Out32(0xFD40D93C, 0xF3); 739 Xil_Out32(0xFD40D914, 0xF3); 740 Xil_Out32(0xFD40D940, 0xF3); 741 } 742 743 if (sata_gen2 == 1) { 744 if (lane0_protocol == 2) { 745 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD402360); 746 Xil_Out32(0xFD402360, 0x0); 747 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410000); 748 psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000DU); 749 temp_TM_IQ_ILL1 = Xil_In32(0xFD4018F8); 750 temp_TM_E_ILL1 = Xil_In32(0xFD401924); 751 Xil_Out32(0xFD4018F8, 0x78); 752 temp_tx_dig_tm_61 = Xil_In32(0xFD4000F4); 753 temp_tm_dig_6 = Xil_In32(0xFD40106C); 754 psu_mask_write(0xFD4000F4, 0x0000000BU, 0x00000000U); 755 psu_mask_write(0xFD40106C, 0x0000000FU, 0x00000000U); 756 temp_ill12 = Xil_In32(0xFD401990) & 0xF0; 757 758 serdes_illcalib_pcie_gen1(0, 0, 0, 0, 0, 0, 0, 1, 0, 0); 759 760 Xil_Out32(0xFD402360, temp_pll_fbdiv_frac_3_msb_offset); 761 Xil_Out32(0xFD410000, temp_PLL_REF_SEL_OFFSET); 762 Xil_Out32(0xFD4018F8, temp_TM_IQ_ILL1); 763 Xil_Out32(0xFD4000F4, temp_tx_dig_tm_61); 764 Xil_Out32(0xFD40106C, temp_tm_dig_6); 765 Xil_Out32(0xFD401928, Xil_In32(0xFD401924)); 766 temp_ill12 = 767 temp_ill12 | (Xil_In32(0xFD401990) >> 4 & 0xF); 768 Xil_Out32(0xFD401990, temp_ill12); 769 Xil_Out32(0xFD401924, temp_TM_E_ILL1); 770 } 771 if (lane1_protocol == 2) { 772 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD406360); 773 Xil_Out32(0xFD406360, 0x0); 774 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410004); 775 psu_mask_write(0xFD410004, 0x0000001FU, 0x0000000DU); 776 temp_TM_IQ_ILL1 = Xil_In32(0xFD4058F8); 777 temp_TM_E_ILL1 = Xil_In32(0xFD405924); 778 Xil_Out32(0xFD4058F8, 0x78); 779 temp_tx_dig_tm_61 = Xil_In32(0xFD4040F4); 780 temp_tm_dig_6 = Xil_In32(0xFD40506C); 781 psu_mask_write(0xFD4040F4, 0x0000000BU, 0x00000000U); 782 psu_mask_write(0xFD40506C, 0x0000000FU, 0x00000000U); 783 temp_ill12 = Xil_In32(0xFD405990) & 0xF0; 784 785 serdes_illcalib_pcie_gen1(1, 0, 0, 0, 0, 1, 0, 0, 0, 0); 786 787 Xil_Out32(0xFD406360, temp_pll_fbdiv_frac_3_msb_offset); 788 Xil_Out32(0xFD410004, temp_PLL_REF_SEL_OFFSET); 789 Xil_Out32(0xFD4058F8, temp_TM_IQ_ILL1); 790 Xil_Out32(0xFD4040F4, temp_tx_dig_tm_61); 791 Xil_Out32(0xFD40506C, temp_tm_dig_6); 792 Xil_Out32(0xFD405928, Xil_In32(0xFD405924)); 793 temp_ill12 = 794 temp_ill12 | (Xil_In32(0xFD405990) >> 4 & 0xF); 795 Xil_Out32(0xFD405990, temp_ill12); 796 Xil_Out32(0xFD405924, temp_TM_E_ILL1); 797 } 798 if (lane2_protocol == 2) { 799 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40A360); 800 Xil_Out32(0xFD40A360, 0x0); 801 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD410008); 802 psu_mask_write(0xFD410008, 0x0000001FU, 0x0000000DU); 803 temp_TM_IQ_ILL1 = Xil_In32(0xFD4098F8); 804 temp_TM_E_ILL1 = Xil_In32(0xFD409924); 805 Xil_Out32(0xFD4098F8, 0x78); 806 temp_tx_dig_tm_61 = Xil_In32(0xFD4080F4); 807 temp_tm_dig_6 = Xil_In32(0xFD40906C); 808 psu_mask_write(0xFD4080F4, 0x0000000BU, 0x00000000U); 809 psu_mask_write(0xFD40906C, 0x0000000FU, 0x00000000U); 810 temp_ill12 = Xil_In32(0xFD409990) & 0xF0; 811 812 serdes_illcalib_pcie_gen1(2, 0, 0, 1, 0, 0, 0, 0, 0, 0); 813 814 Xil_Out32(0xFD40A360, temp_pll_fbdiv_frac_3_msb_offset); 815 Xil_Out32(0xFD410008, temp_PLL_REF_SEL_OFFSET); 816 Xil_Out32(0xFD4098F8, temp_TM_IQ_ILL1); 817 Xil_Out32(0xFD4080F4, temp_tx_dig_tm_61); 818 Xil_Out32(0xFD40906C, temp_tm_dig_6); 819 Xil_Out32(0xFD409928, Xil_In32(0xFD409924)); 820 temp_ill12 = 821 temp_ill12 | (Xil_In32(0xFD409990) >> 4 & 0xF); 822 Xil_Out32(0xFD409990, temp_ill12); 823 Xil_Out32(0xFD409924, temp_TM_E_ILL1); 824 } 825 if (lane3_protocol == 2) { 826 temp_pll_fbdiv_frac_3_msb_offset = Xil_In32(0xFD40E360); 827 Xil_Out32(0xFD40E360, 0x0); 828 temp_PLL_REF_SEL_OFFSET = Xil_In32(0xFD41000C); 829 psu_mask_write(0xFD41000C, 0x0000001FU, 0x0000000DU); 830 temp_TM_IQ_ILL1 = Xil_In32(0xFD40D8F8); 831 temp_TM_E_ILL1 = Xil_In32(0xFD40D924); 832 Xil_Out32(0xFD40D8F8, 0x78); 833 temp_tx_dig_tm_61 = Xil_In32(0xFD40C0F4); 834 temp_tm_dig_6 = Xil_In32(0xFD40D06C); 835 psu_mask_write(0xFD40C0F4, 0x0000000BU, 0x00000000U); 836 psu_mask_write(0xFD40D06C, 0x0000000FU, 0x00000000U); 837 temp_ill12 = Xil_In32(0xFD40D990) & 0xF0; 838 839 serdes_illcalib_pcie_gen1(3, 1, 0, 0, 0, 0, 0, 0, 0, 0); 840 841 Xil_Out32(0xFD40E360, temp_pll_fbdiv_frac_3_msb_offset); 842 Xil_Out32(0xFD41000C, temp_PLL_REF_SEL_OFFSET); 843 Xil_Out32(0xFD40D8F8, temp_TM_IQ_ILL1); 844 Xil_Out32(0xFD40C0F4, temp_tx_dig_tm_61); 845 Xil_Out32(0xFD40D06C, temp_tm_dig_6); 846 Xil_Out32(0xFD40D928, Xil_In32(0xFD40D924)); 847 temp_ill12 = 848 temp_ill12 | (Xil_In32(0xFD40D990) >> 4 & 0xF); 849 Xil_Out32(0xFD40D990, temp_ill12); 850 Xil_Out32(0xFD40D924, temp_TM_E_ILL1); 851 } 852 rdata = Xil_In32(0xFD410098); 853 rdata = (rdata & 0xDF); 854 Xil_Out32(0xFD410098, rdata); 855 } 856 857 if (lane0_protocol == 2 && lane0_rate == 3) { 858 psu_mask_write(0xFD40198C, 0x000000F0U, 0x00000020U); 859 psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000094U); 860 } 861 if (lane1_protocol == 2 && lane1_rate == 3) { 862 psu_mask_write(0xFD40598C, 0x000000F0U, 0x00000020U); 863 psu_mask_write(0xFD40592C, 0x000000FFU, 0x00000094U); 864 } 865 if (lane2_protocol == 2 && lane2_rate == 3) { 866 psu_mask_write(0xFD40998C, 0x000000F0U, 0x00000020U); 867 psu_mask_write(0xFD40992C, 0x000000FFU, 0x00000094U); 868 } 869 if (lane3_protocol == 2 && lane3_rate == 3) { 870 psu_mask_write(0xFD40D98C, 0x000000F0U, 0x00000020U); 871 psu_mask_write(0xFD40D92C, 0x000000FFU, 0x00000094U); 872 } 873 874 if (lane0_protocol == 1) { 875 if (lane0_rate == 0) { 876 serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, 877 lane2_protocol, lane2_rate, 878 lane1_protocol, lane1_rate, 879 lane0_protocol, 0, 0); 880 } else { 881 serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, 882 lane2_protocol, lane2_rate, 883 lane1_protocol, lane1_rate, 884 lane0_protocol, 0, 0); 885 serdes_illcalib_pcie_gen1(0, lane3_protocol, lane3_rate, 886 lane2_protocol, lane2_rate, 887 lane1_protocol, lane1_rate, 888 lane0_protocol, lane0_rate, 889 1); 890 } 891 } 892 893 if (lane0_protocol == 3) 894 Xil_Out32(0xFD401914, 0xF3); 895 if (lane0_protocol == 3) 896 Xil_Out32(0xFD401940, 0xF3); 897 if (lane0_protocol == 3) 898 Xil_Out32(0xFD401990, 0x20); 899 if (lane0_protocol == 3) 900 Xil_Out32(0xFD401924, 0x37); 901 902 if (lane1_protocol == 3) 903 Xil_Out32(0xFD405914, 0xF3); 904 if (lane1_protocol == 3) 905 Xil_Out32(0xFD405940, 0xF3); 906 if (lane1_protocol == 3) 907 Xil_Out32(0xFD405990, 0x20); 908 if (lane1_protocol == 3) 909 Xil_Out32(0xFD405924, 0x37); 910 911 if (lane2_protocol == 3) 912 Xil_Out32(0xFD409914, 0xF3); 913 if (lane2_protocol == 3) 914 Xil_Out32(0xFD409940, 0xF3); 915 if (lane2_protocol == 3) 916 Xil_Out32(0xFD409990, 0x20); 917 if (lane2_protocol == 3) 918 Xil_Out32(0xFD409924, 0x37); 919 920 if (lane3_protocol == 3) 921 Xil_Out32(0xFD40D914, 0xF3); 922 if (lane3_protocol == 3) 923 Xil_Out32(0xFD40D940, 0xF3); 924 if (lane3_protocol == 3) 925 Xil_Out32(0xFD40D990, 0x20); 926 if (lane3_protocol == 3) 927 Xil_Out32(0xFD40D924, 0x37); 928 929 return 1; 930} 931 932static void dpll_prog(int div2, int ddr_pll_fbdiv, int d_lock_dly, 933 int d_lock_cnt, int d_lfhf, int d_cp, int d_res) 934{ 935 unsigned int pll_ctrl_regval; 936 unsigned int pll_status_regval; 937 938 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); 939 pll_ctrl_regval = pll_ctrl_regval & (~0x00010000U); 940 pll_ctrl_regval = pll_ctrl_regval | (div2 << 16); 941 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); 942 943 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); 944 pll_ctrl_regval = pll_ctrl_regval & (~0xFE000000U); 945 pll_ctrl_regval = pll_ctrl_regval | (d_lock_dly << 25); 946 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); 947 948 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); 949 pll_ctrl_regval = pll_ctrl_regval & (~0x007FE000U); 950 pll_ctrl_regval = pll_ctrl_regval | (d_lock_cnt << 13); 951 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); 952 953 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); 954 pll_ctrl_regval = pll_ctrl_regval & (~0x00000C00U); 955 pll_ctrl_regval = pll_ctrl_regval | (d_lfhf << 10); 956 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); 957 958 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); 959 pll_ctrl_regval = pll_ctrl_regval & (~0x000001E0U); 960 pll_ctrl_regval = pll_ctrl_regval | (d_cp << 5); 961 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); 962 963 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x00000030)); 964 pll_ctrl_regval = pll_ctrl_regval & (~0x0000000FU); 965 pll_ctrl_regval = pll_ctrl_regval | (d_res << 0); 966 Xil_Out32(((0xFD1A0000U) + 0x00000030), pll_ctrl_regval); 967 968 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); 969 pll_ctrl_regval = pll_ctrl_regval & (~0x00007F00U); 970 pll_ctrl_regval = pll_ctrl_regval | (ddr_pll_fbdiv << 8); 971 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); 972 973 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); 974 pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); 975 pll_ctrl_regval = pll_ctrl_regval | (1 << 3); 976 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); 977 978 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); 979 pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); 980 pll_ctrl_regval = pll_ctrl_regval | (1 << 0); 981 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); 982 983 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); 984 pll_ctrl_regval = pll_ctrl_regval & (~0x00000001U); 985 pll_ctrl_regval = pll_ctrl_regval | (0 << 0); 986 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); 987 988 pll_status_regval = 0x00000000; 989 while ((pll_status_regval & 0x00000002U) != 0x00000002U) 990 pll_status_regval = Xil_In32(((0xFD1A0000U) + 0x00000044)); 991 992 pll_ctrl_regval = Xil_In32(((0xFD1A0000U) + 0x0000002C)); 993 pll_ctrl_regval = pll_ctrl_regval & (~0x00000008U); 994 pll_ctrl_regval = pll_ctrl_regval | (0 << 3); 995 Xil_Out32(((0xFD1A0000U) + 0x0000002C), pll_ctrl_regval); 996} 997 998static unsigned long psu_pll_init_data(void) 999{ 1000 psu_mask_write(0xFF5E0034, 0xFE7FEDEFU, 0x7E4B0C62U); 1001 psu_mask_write(0xFF5E0030, 0x00717F00U, 0x00014600U); 1002 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000008U); 1003 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000001U); 1004 psu_mask_write(0xFF5E0030, 0x00000001U, 0x00000000U); 1005 mask_poll(0xFF5E0040, 0x00000002U); 1006 psu_mask_write(0xFF5E0030, 0x00000008U, 0x00000000U); 1007 psu_mask_write(0xFF5E0048, 0x00003F00U, 0x00000300U); 1008 psu_mask_write(0xFF5E0038, 0x8000FFFFU, 0x00000000U); 1009 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012300U); 1010 psu_mask_write(0xFF5E0024, 0xFE7FEDEFU, 0x7E672C6CU); 1011 psu_mask_write(0xFF5E0020, 0x00717F00U, 0x00002D00U); 1012 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000008U); 1013 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000001U); 1014 psu_mask_write(0xFF5E0020, 0x00000001U, 0x00000000U); 1015 mask_poll(0xFF5E0040, 0x00000001U); 1016 psu_mask_write(0xFF5E0020, 0x00000008U, 0x00000000U); 1017 psu_mask_write(0xFF5E0044, 0x00003F00U, 0x00000300U); 1018 psu_mask_write(0xFF5E0028, 0x8000FFFFU, 0x00000000U); 1019 psu_mask_write(0xFD1A0024, 0xFE7FEDEFU, 0x7E4B0C62U); 1020 psu_mask_write(0xFD1A0020, 0x00717F00U, 0x00014800U); 1021 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000008U); 1022 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000001U); 1023 psu_mask_write(0xFD1A0020, 0x00000001U, 0x00000000U); 1024 mask_poll(0xFD1A0044, 0x00000001U); 1025 psu_mask_write(0xFD1A0020, 0x00000008U, 0x00000000U); 1026 psu_mask_write(0xFD1A0048, 0x00003F00U, 0x00000300U); 1027 psu_mask_write(0xFD1A0028, 0x8000FFFFU, 0x00000000U); 1028 psu_mask_write(0xFD1A0030, 0xFE7FEDEFU, 0x7E4B0C62U); 1029 psu_mask_write(0xFD1A002C, 0x00717F00U, 0x00014000U); 1030 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000008U); 1031 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000001U); 1032 psu_mask_write(0xFD1A002C, 0x00000001U, 0x00000000U); 1033 mask_poll(0xFD1A0044, 0x00000002U); 1034 psu_mask_write(0xFD1A002C, 0x00000008U, 0x00000000U); 1035 psu_mask_write(0xFD1A004C, 0x00003F00U, 0x00000300U); 1036 psu_mask_write(0xFD1A0034, 0x8000FFFFU, 0x00000000U); 1037 psu_mask_write(0xFD1A003C, 0xFE7FEDEFU, 0x7E4B0C62U); 1038 psu_mask_write(0xFD1A0038, 0x00717F00U, 0x00014700U); 1039 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000008U); 1040 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000001U); 1041 psu_mask_write(0xFD1A0038, 0x00000001U, 0x00000000U); 1042 mask_poll(0xFD1A0044, 0x00000004U); 1043 psu_mask_write(0xFD1A0038, 0x00000008U, 0x00000000U); 1044 psu_mask_write(0xFD1A0050, 0x00003F00U, 0x00000300U); 1045 psu_mask_write(0xFD1A0040, 0x8000FFFFU, 0x00000000U); 1046 1047 return 1; 1048} 1049 1050static unsigned long psu_clock_init_data(void) 1051{ 1052 psu_mask_write(0xFF5E0050, 0x063F3F07U, 0x06010C00U); 1053 psu_mask_write(0xFF180360, 0x00000003U, 0x00000001U); 1054 psu_mask_write(0xFF180308, 0x00000006U, 0x00000006U); 1055 psu_mask_write(0xFF5E0100, 0x013F3F07U, 0x01010600U); 1056 psu_mask_write(0xFF5E0070, 0x013F3F07U, 0x01010800U); 1057 psu_mask_write(0xFF18030C, 0x00020000U, 0x00000000U); 1058 psu_mask_write(0xFF5E0074, 0x013F3F07U, 0x01010F00U); 1059 psu_mask_write(0xFF5E0120, 0x013F3F07U, 0x01010F00U); 1060 psu_mask_write(0xFF5E0124, 0x013F3F07U, 0x01010F00U); 1061 psu_mask_write(0xFF5E0090, 0x01003F07U, 0x01000302U); 1062 psu_mask_write(0xFF5E009C, 0x01003F07U, 0x01000602U); 1063 psu_mask_write(0xFF5E00A4, 0x01003F07U, 0x01000800U); 1064 psu_mask_write(0xFF5E00A8, 0x01003F07U, 0x01000302U); 1065 psu_mask_write(0xFF5E00AC, 0x01003F07U, 0x01000F02U); 1066 psu_mask_write(0xFF5E00B0, 0x01003F07U, 0x01000602U); 1067 psu_mask_write(0xFF5E00B8, 0x01003F07U, 0x01000302U); 1068 psu_mask_write(0xFF5E00C0, 0x013F3F07U, 0x01010F00U); 1069 psu_mask_write(0xFF5E00C4, 0x013F3F07U, 0x01040F00U); 1070 psu_mask_write(0xFF5E00C8, 0x013F3F07U, 0x01010500U); 1071 psu_mask_write(0xFF5E00CC, 0x013F3F07U, 0x01010400U); 1072 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01011D02U); 1073 psu_mask_write(0xFF5E0104, 0x00000007U, 0x00000000U); 1074 psu_mask_write(0xFF5E0128, 0x01003F07U, 0x01000F00U); 1075 psu_mask_write(0xFD1A0060, 0x03003F07U, 0x03000100U); 1076 psu_mask_write(0xFD1A0068, 0x01003F07U, 0x01000200U); 1077 psu_mask_write(0xFD1A0080, 0x00003F07U, 0x00000200U); 1078 psu_mask_write(0xFD1A0084, 0x07003F07U, 0x07000100U); 1079 psu_mask_write(0xFD1A00B8, 0x01003F07U, 0x01000200U); 1080 psu_mask_write(0xFD1A00BC, 0x01003F07U, 0x01000200U); 1081 psu_mask_write(0xFD1A00C0, 0x01003F07U, 0x01000203U); 1082 psu_mask_write(0xFD1A00C4, 0x01003F07U, 0x01000502U); 1083 psu_mask_write(0xFD1A00F8, 0x00003F07U, 0x00000200U); 1084 psu_mask_write(0xFF180380, 0x000000FFU, 0x00000000U); 1085 psu_mask_write(0xFD610100, 0x00000001U, 0x00000000U); 1086 psu_mask_write(0xFF180300, 0x00000001U, 0x00000000U); 1087 psu_mask_write(0xFF410050, 0x00000001U, 0x00000000U); 1088 1089 return 1; 1090} 1091 1092static unsigned long psu_ddr_init_data(void) 1093{ 1094 psu_mask_write(0xFD1A0108, 0x00000008U, 0x00000008U); 1095 psu_mask_write(0xFD070000, 0xE30FBE3DU, 0xC1081020U); 1096 psu_mask_write(0xFD070010, 0x8000F03FU, 0x00000030U); 1097 psu_mask_write(0xFD070020, 0x000003F3U, 0x00000202U); 1098 psu_mask_write(0xFD070024, 0xFFFFFFFFU, 0x00516120U); 1099 psu_mask_write(0xFD070030, 0x0000007FU, 0x00000000U); 1100 psu_mask_write(0xFD070034, 0x00FFFF1FU, 0x00408410U); 1101 psu_mask_write(0xFD070050, 0x00F1F1F4U, 0x00210000U); 1102 psu_mask_write(0xFD070054, 0x0FFF0FFFU, 0x00000000U); 1103 psu_mask_write(0xFD070060, 0x00000073U, 0x00000001U); 1104 psu_mask_write(0xFD070064, 0x0FFF83FFU, 0x00418096U); 1105 psu_mask_write(0xFD070070, 0x00000017U, 0x00000010U); 1106 psu_mask_write(0xFD070074, 0x00000003U, 0x00000000U); 1107 psu_mask_write(0xFD0700C4, 0x3F000391U, 0x10000200U); 1108 psu_mask_write(0xFD0700C8, 0x01FF1F3FU, 0x0030051FU); 1109 psu_mask_write(0xFD0700D0, 0xC3FF0FFFU, 0x00030413U); 1110 psu_mask_write(0xFD0700D4, 0x01FF7F0FU, 0x006A0000U); 1111 psu_mask_write(0xFD0700D8, 0x0000FF0FU, 0x00002305U); 1112 psu_mask_write(0xFD0700DC, 0xFFFFFFFFU, 0x00440024U); 1113 psu_mask_write(0xFD0700E0, 0xFFFFFFFFU, 0x00310008U); 1114 psu_mask_write(0xFD0700E4, 0x00FF03FFU, 0x00210004U); 1115 psu_mask_write(0xFD0700E8, 0xFFFFFFFFU, 0x00000000U); 1116 psu_mask_write(0xFD0700EC, 0xFFFF0000U, 0x00000000U); 1117 psu_mask_write(0xFD0700F0, 0x0000003FU, 0x00000010U); 1118 psu_mask_write(0xFD0700F4, 0x00000FFFU, 0x0000077FU); 1119 psu_mask_write(0xFD070100, 0x7F3F7F3FU, 0x15161117U); 1120 psu_mask_write(0xFD070104, 0x001F1F7FU, 0x00040422U); 1121 psu_mask_write(0xFD070108, 0x3F3F3F3FU, 0x060C1A10U); 1122 psu_mask_write(0xFD07010C, 0x3FF3F3FFU, 0x00F08000U); 1123 psu_mask_write(0xFD070110, 0x1F0F0F1FU, 0x0A04060CU); 1124 psu_mask_write(0xFD070114, 0x0F0F3F1FU, 0x01040808U); 1125 psu_mask_write(0xFD070118, 0x0F0F000FU, 0x01010005U); 1126 psu_mask_write(0xFD07011C, 0x00000F0FU, 0x00000401U); 1127 psu_mask_write(0xFD070120, 0x7F7F7F7FU, 0x04040606U); 1128 psu_mask_write(0xFD070124, 0x40070F3FU, 0x0004040DU); 1129 psu_mask_write(0xFD07012C, 0x7F1F031FU, 0x440C011CU); 1130 psu_mask_write(0xFD070130, 0x00030F1FU, 0x00020608U); 1131 psu_mask_write(0xFD070180, 0xF7FF03FFU, 0x82160010U); 1132 psu_mask_write(0xFD070184, 0x3FFFFFFFU, 0x01B65B96U); 1133 psu_mask_write(0xFD070190, 0x1FBFBF3FU, 0x0495820AU); 1134 psu_mask_write(0xFD070194, 0xF31F0F0FU, 0x00030304U); 1135 psu_mask_write(0xFD070198, 0x0FF1F1F1U, 0x07000101U); 1136 psu_mask_write(0xFD07019C, 0x000000F1U, 0x00000021U); 1137 psu_mask_write(0xFD0701A0, 0xC3FF03FFU, 0x83FF0003U); 1138 psu_mask_write(0xFD0701A4, 0x00FF00FFU, 0x00C800FFU); 1139 psu_mask_write(0xFD0701B0, 0x00000007U, 0x00000004U); 1140 psu_mask_write(0xFD0701B4, 0x00003F3FU, 0x00001308U); 1141 psu_mask_write(0xFD0701C0, 0x00000007U, 0x00000001U); 1142 psu_mask_write(0xFD070200, 0x0000001FU, 0x0000001FU); 1143 psu_mask_write(0xFD070204, 0x001F1F1FU, 0x00070707U); 1144 psu_mask_write(0xFD070208, 0x0F0F0F0FU, 0x00000000U); 1145 psu_mask_write(0xFD07020C, 0x0F0F0F0FU, 0x0F000000U); 1146 psu_mask_write(0xFD070210, 0x00000F0FU, 0x00000F0FU); 1147 psu_mask_write(0xFD070214, 0x0F0F0F0FU, 0x060F0606U); 1148 psu_mask_write(0xFD070218, 0x8F0F0F0FU, 0x06060606U); 1149 psu_mask_write(0xFD07021C, 0x00000F0FU, 0x00000F0FU); 1150 psu_mask_write(0xFD070220, 0x00001F1FU, 0x00000000U); 1151 psu_mask_write(0xFD070224, 0x0F0F0F0FU, 0x06060606U); 1152 psu_mask_write(0xFD070228, 0x0F0F0F0FU, 0x06060606U); 1153 psu_mask_write(0xFD07022C, 0x0000000FU, 0x00000006U); 1154 psu_mask_write(0xFD070240, 0x0F1F0F7CU, 0x04000400U); 1155 psu_mask_write(0xFD070244, 0x00003333U, 0x00000000U); 1156 psu_mask_write(0xFD070250, 0x7FFF3F07U, 0x01002001U); 1157 psu_mask_write(0xFD070264, 0xFF00FFFFU, 0x08000040U); 1158 psu_mask_write(0xFD07026C, 0xFF00FFFFU, 0x08000040U); 1159 psu_mask_write(0xFD070280, 0xFFFFFFFFU, 0x00000000U); 1160 psu_mask_write(0xFD070284, 0xFFFFFFFFU, 0x00000000U); 1161 psu_mask_write(0xFD070288, 0xFFFFFFFFU, 0x00000000U); 1162 psu_mask_write(0xFD07028C, 0xFFFFFFFFU, 0x00000000U); 1163 psu_mask_write(0xFD070290, 0x0000FFFFU, 0x00000000U); 1164 psu_mask_write(0xFD070294, 0x00000001U, 0x00000001U); 1165 psu_mask_write(0xFD070300, 0x00000011U, 0x00000000U); 1166 psu_mask_write(0xFD07030C, 0x80000033U, 0x00000000U); 1167 psu_mask_write(0xFD070320, 0x00000001U, 0x00000000U); 1168 psu_mask_write(0xFD070400, 0x00000111U, 0x00000001U); 1169 psu_mask_write(0xFD070404, 0x000073FFU, 0x0000200FU); 1170 psu_mask_write(0xFD070408, 0x000073FFU, 0x0000200FU); 1171 psu_mask_write(0xFD070490, 0x00000001U, 0x00000001U); 1172 psu_mask_write(0xFD070494, 0x0033000FU, 0x0020000BU); 1173 psu_mask_write(0xFD070498, 0x07FF07FFU, 0x00000000U); 1174 psu_mask_write(0xFD0704B4, 0x000073FFU, 0x0000200FU); 1175 psu_mask_write(0xFD0704B8, 0x000073FFU, 0x0000200FU); 1176 psu_mask_write(0xFD070540, 0x00000001U, 0x00000001U); 1177 psu_mask_write(0xFD070544, 0x03330F0FU, 0x02000B03U); 1178 psu_mask_write(0xFD070548, 0x07FF07FFU, 0x00000000U); 1179 psu_mask_write(0xFD070564, 0x000073FFU, 0x0000200FU); 1180 psu_mask_write(0xFD070568, 0x000073FFU, 0x0000200FU); 1181 psu_mask_write(0xFD0705F0, 0x00000001U, 0x00000001U); 1182 psu_mask_write(0xFD0705F4, 0x03330F0FU, 0x02000B03U); 1183 psu_mask_write(0xFD0705F8, 0x07FF07FFU, 0x00000000U); 1184 psu_mask_write(0xFD070614, 0x000073FFU, 0x0000200FU); 1185 psu_mask_write(0xFD070618, 0x000073FFU, 0x0000200FU); 1186 psu_mask_write(0xFD0706A0, 0x00000001U, 0x00000001U); 1187 psu_mask_write(0xFD0706A4, 0x0033000FU, 0x00100003U); 1188 psu_mask_write(0xFD0706A8, 0x07FF07FFU, 0x0000004FU); 1189 psu_mask_write(0xFD0706AC, 0x0033000FU, 0x00100003U); 1190 psu_mask_write(0xFD0706B0, 0x000007FFU, 0x0000004FU); 1191 psu_mask_write(0xFD0706C4, 0x000073FFU, 0x0000200FU); 1192 psu_mask_write(0xFD0706C8, 0x000073FFU, 0x0000200FU); 1193 psu_mask_write(0xFD070750, 0x00000001U, 0x00000001U); 1194 psu_mask_write(0xFD070754, 0x0033000FU, 0x00100003U); 1195 psu_mask_write(0xFD070758, 0x07FF07FFU, 0x0000004FU); 1196 psu_mask_write(0xFD07075C, 0x0033000FU, 0x00100003U); 1197 psu_mask_write(0xFD070760, 0x000007FFU, 0x0000004FU); 1198 psu_mask_write(0xFD070774, 0x000073FFU, 0x0000200FU); 1199 psu_mask_write(0xFD070778, 0x000073FFU, 0x0000200FU); 1200 psu_mask_write(0xFD070800, 0x00000001U, 0x00000001U); 1201 psu_mask_write(0xFD070804, 0x0033000FU, 0x00100003U); 1202 psu_mask_write(0xFD070808, 0x07FF07FFU, 0x0000004FU); 1203 psu_mask_write(0xFD07080C, 0x0033000FU, 0x00100003U); 1204 psu_mask_write(0xFD070810, 0x000007FFU, 0x0000004FU); 1205 psu_mask_write(0xFD070F04, 0x000001FFU, 0x00000000U); 1206 psu_mask_write(0xFD070F08, 0x000000FFU, 0x00000000U); 1207 psu_mask_write(0xFD070F0C, 0x000001FFU, 0x00000010U); 1208 psu_mask_write(0xFD070F10, 0x000000FFU, 0x0000000FU); 1209 psu_mask_write(0xFD072190, 0x1FBFBF3FU, 0x07828002U); 1210 psu_mask_write(0xFD1A0108, 0x0000000CU, 0x00000000U); 1211 psu_mask_write(0xFD080010, 0xFFFFFFFFU, 0x87001E00U); 1212 psu_mask_write(0xFD080018, 0xFFFFFFFFU, 0x00F07E38U); 1213 psu_mask_write(0xFD08001C, 0xFFFFFFFFU, 0x55AA5480U); 1214 psu_mask_write(0xFD080024, 0xFFFFFFFFU, 0x010100F4U); 1215 psu_mask_write(0xFD080040, 0xFFFFFFFFU, 0x42C21590U); 1216 psu_mask_write(0xFD080044, 0xFFFFFFFFU, 0xD05512C0U); 1217 psu_mask_write(0xFD080068, 0xFFFFFFFFU, 0x01100000U); 1218 psu_mask_write(0xFD080090, 0xFFFFFFFFU, 0x02A04161U); 1219 psu_mask_write(0xFD0800C0, 0xFFFFFFFFU, 0x00000000U); 1220 psu_mask_write(0xFD0800C4, 0xFFFFFFFFU, 0x000000E4U); 1221 psu_mask_write(0xFD080100, 0xFFFFFFFFU, 0x0000040DU); 1222 psu_mask_write(0xFD080110, 0xFFFFFFFFU, 0x0B2E1708U); 1223 psu_mask_write(0xFD080114, 0xFFFFFFFFU, 0x282B0711U); 1224 psu_mask_write(0xFD080118, 0xFFFFFFFFU, 0x000F0133U); 1225 psu_mask_write(0xFD08011C, 0xFFFFFFFFU, 0x82000501U); 1226 psu_mask_write(0xFD080120, 0xFFFFFFFFU, 0x012B2B0BU); 1227 psu_mask_write(0xFD080124, 0xFFFFFFFFU, 0x0044260BU); 1228 psu_mask_write(0xFD080128, 0xFFFFFFFFU, 0x00000C18U); 1229 psu_mask_write(0xFD080140, 0xFFFFFFFFU, 0x08400020U); 1230 psu_mask_write(0xFD080144, 0xFFFFFFFFU, 0x00000C80U); 1231 psu_mask_write(0xFD080150, 0xFFFFFFFFU, 0x00000000U); 1232 psu_mask_write(0xFD080154, 0xFFFFFFFFU, 0x00000000U); 1233 psu_mask_write(0xFD080180, 0xFFFFFFFFU, 0x00000000U); 1234 psu_mask_write(0xFD080184, 0xFFFFFFFFU, 0x00000044U); 1235 psu_mask_write(0xFD080188, 0xFFFFFFFFU, 0x00000024U); 1236 psu_mask_write(0xFD08018C, 0xFFFFFFFFU, 0x00000031U); 1237 psu_mask_write(0xFD080190, 0xFFFFFFFFU, 0x00000008U); 1238 psu_mask_write(0xFD080194, 0xFFFFFFFFU, 0x00000000U); 1239 psu_mask_write(0xFD080198, 0xFFFFFFFFU, 0x00000000U); 1240 psu_mask_write(0xFD0801AC, 0xFFFFFFFFU, 0x00000056U); 1241 psu_mask_write(0xFD0801B0, 0xFFFFFFFFU, 0x00000056U); 1242 psu_mask_write(0xFD0801B4, 0xFFFFFFFFU, 0x00000008U); 1243 psu_mask_write(0xFD0801B8, 0xFFFFFFFFU, 0x00000019U); 1244 psu_mask_write(0xFD0801D8, 0xFFFFFFFFU, 0x00000016U); 1245 psu_mask_write(0xFD080200, 0xFFFFFFFFU, 0x800091C7U); 1246 psu_mask_write(0xFD080204, 0xFFFFFFFFU, 0x00010236U); 1247 psu_mask_write(0xFD080240, 0xFFFFFFFFU, 0x00141054U); 1248 psu_mask_write(0xFD080250, 0xFFFFFFFFU, 0x00088000U); 1249 psu_mask_write(0xFD080414, 0xFFFFFFFFU, 0x12340800U); 1250 psu_mask_write(0xFD0804F4, 0xFFFFFFFFU, 0x0000000AU); 1251 psu_mask_write(0xFD080500, 0xFFFFFFFFU, 0x30000028U); 1252 psu_mask_write(0xFD080508, 0xFFFFFFFFU, 0x00000000U); 1253 psu_mask_write(0xFD08050C, 0xFFFFFFFFU, 0x00000005U); 1254 psu_mask_write(0xFD080510, 0xFFFFFFFFU, 0x00000000U); 1255 psu_mask_write(0xFD080520, 0xFFFFFFFFU, 0x0300BD99U); 1256 psu_mask_write(0xFD080528, 0xFFFFFFFFU, 0xF1032019U); 1257 psu_mask_write(0xFD08052C, 0xFFFFFFFFU, 0x07F001E3U); 1258 psu_mask_write(0xFD080544, 0xFFFFFFFFU, 0x00000000U); 1259 psu_mask_write(0xFD080548, 0xFFFFFFFFU, 0x00000000U); 1260 psu_mask_write(0xFD080558, 0xFFFFFFFFU, 0x00000000U); 1261 psu_mask_write(0xFD08055C, 0xFFFFFFFFU, 0x00000000U); 1262 psu_mask_write(0xFD080560, 0xFFFFFFFFU, 0x00000000U); 1263 psu_mask_write(0xFD080564, 0xFFFFFFFFU, 0x00000000U); 1264 psu_mask_write(0xFD080680, 0xFFFFFFFFU, 0x008AAC58U); 1265 psu_mask_write(0xFD080684, 0xFFFFFFFFU, 0x0001B39BU); 1266 psu_mask_write(0xFD080694, 0xFFFFFFFFU, 0x01E10210U); 1267 psu_mask_write(0xFD080698, 0xFFFFFFFFU, 0x01E10000U); 1268 psu_mask_write(0xFD0806A4, 0xFFFFFFFFU, 0x0001BB9BU); 1269 psu_mask_write(0xFD080700, 0xFFFFFFFFU, 0x40800604U); 1270 psu_mask_write(0xFD080704, 0xFFFFFFFFU, 0x00007FFFU); 1271 psu_mask_write(0xFD08070C, 0xFFFFFFFFU, 0x3F000008U); 1272 psu_mask_write(0xFD080710, 0xFFFFFFFFU, 0x0E00F50CU); 1273 psu_mask_write(0xFD080714, 0xFFFFFFFFU, 0x09091616U); 1274 psu_mask_write(0xFD080718, 0xFFFFFFFFU, 0x09092B2BU); 1275 psu_mask_write(0xFD080800, 0xFFFFFFFFU, 0x40800604U); 1276 psu_mask_write(0xFD080804, 0xFFFFFFFFU, 0x00007FFFU); 1277 psu_mask_write(0xFD08080C, 0xFFFFFFFFU, 0x3F000008U); 1278 psu_mask_write(0xFD080810, 0xFFFFFFFFU, 0x0E00F50CU); 1279 psu_mask_write(0xFD080814, 0xFFFFFFFFU, 0x09091616U); 1280 psu_mask_write(0xFD080818, 0xFFFFFFFFU, 0x09092B2BU); 1281 psu_mask_write(0xFD080900, 0xFFFFFFFFU, 0x40800604U); 1282 psu_mask_write(0xFD080904, 0xFFFFFFFFU, 0x00007FFFU); 1283 psu_mask_write(0xFD08090C, 0xFFFFFFFFU, 0x3F000008U); 1284 psu_mask_write(0xFD080910, 0xFFFFFFFFU, 0x0E00F504U); 1285 psu_mask_write(0xFD080914, 0xFFFFFFFFU, 0x09091616U); 1286 psu_mask_write(0xFD080918, 0xFFFFFFFFU, 0x09092B2BU); 1287 psu_mask_write(0xFD080A00, 0xFFFFFFFFU, 0x40800604U); 1288 psu_mask_write(0xFD080A04, 0xFFFFFFFFU, 0x00007FFFU); 1289 psu_mask_write(0xFD080A0C, 0xFFFFFFFFU, 0x3F000008U); 1290 psu_mask_write(0xFD080A10, 0xFFFFFFFFU, 0x0E00F504U); 1291 psu_mask_write(0xFD080A14, 0xFFFFFFFFU, 0x09091616U); 1292 psu_mask_write(0xFD080A18, 0xFFFFFFFFU, 0x09092B2BU); 1293 psu_mask_write(0xFD080B00, 0xFFFFFFFFU, 0x80803660U); 1294 psu_mask_write(0xFD080B04, 0xFFFFFFFFU, 0x55556000U); 1295 psu_mask_write(0xFD080B08, 0xFFFFFFFFU, 0xAAAAAAAAU); 1296 psu_mask_write(0xFD080B0C, 0xFFFFFFFFU, 0x0029A4A4U); 1297 psu_mask_write(0xFD080B10, 0xFFFFFFFFU, 0x0C00BD00U); 1298 psu_mask_write(0xFD080B14, 0xFFFFFFFFU, 0x09091616U); 1299 psu_mask_write(0xFD080B18, 0xFFFFFFFFU, 0x09092B2BU); 1300 psu_mask_write(0xFD080C00, 0xFFFFFFFFU, 0x80803660U); 1301 psu_mask_write(0xFD080C04, 0xFFFFFFFFU, 0x55556000U); 1302 psu_mask_write(0xFD080C08, 0xFFFFFFFFU, 0xAAAAAAAAU); 1303 psu_mask_write(0xFD080C0C, 0xFFFFFFFFU, 0x0029A4A4U); 1304 psu_mask_write(0xFD080C10, 0xFFFFFFFFU, 0x0C00BD00U); 1305 psu_mask_write(0xFD080C14, 0xFFFFFFFFU, 0x09091616U); 1306 psu_mask_write(0xFD080C18, 0xFFFFFFFFU, 0x09092B2BU); 1307 psu_mask_write(0xFD080D00, 0xFFFFFFFFU, 0x80803660U); 1308 psu_mask_write(0xFD080D04, 0xFFFFFFFFU, 0x55556000U); 1309 psu_mask_write(0xFD080D08, 0xFFFFFFFFU, 0xAAAAAAAAU); 1310 psu_mask_write(0xFD080D0C, 0xFFFFFFFFU, 0x0029A4A4U); 1311 psu_mask_write(0xFD080D10, 0xFFFFFFFFU, 0x0C00BD00U); 1312 psu_mask_write(0xFD080D14, 0xFFFFFFFFU, 0x09091616U); 1313 psu_mask_write(0xFD080D18, 0xFFFFFFFFU, 0x09092B2BU); 1314 psu_mask_write(0xFD080E00, 0xFFFFFFFFU, 0x80803660U); 1315 psu_mask_write(0xFD080E04, 0xFFFFFFFFU, 0x55556000U); 1316 psu_mask_write(0xFD080E08, 0xFFFFFFFFU, 0xAAAAAAAAU); 1317 psu_mask_write(0xFD080E0C, 0xFFFFFFFFU, 0x0029A4A4U); 1318 psu_mask_write(0xFD080E10, 0xFFFFFFFFU, 0x0C00BD00U); 1319 psu_mask_write(0xFD080E14, 0xFFFFFFFFU, 0x09091616U); 1320 psu_mask_write(0xFD080E18, 0xFFFFFFFFU, 0x09092B2BU); 1321 psu_mask_write(0xFD080F00, 0xFFFFFFFFU, 0x80803660U); 1322 psu_mask_write(0xFD080F04, 0xFFFFFFFFU, 0x55556000U); 1323 psu_mask_write(0xFD080F08, 0xFFFFFFFFU, 0xAAAAAAAAU); 1324 psu_mask_write(0xFD080F0C, 0xFFFFFFFFU, 0x0029A4A4U); 1325 psu_mask_write(0xFD080F10, 0xFFFFFFFFU, 0x0C00BD00U); 1326 psu_mask_write(0xFD080F14, 0xFFFFFFFFU, 0x09091616U); 1327 psu_mask_write(0xFD080F18, 0xFFFFFFFFU, 0x09092B2BU); 1328 psu_mask_write(0xFD081400, 0xFFFFFFFFU, 0x2A019FFEU); 1329 psu_mask_write(0xFD081404, 0xFFFFFFFFU, 0x01100000U); 1330 psu_mask_write(0xFD08141C, 0xFFFFFFFFU, 0x01264300U); 1331 psu_mask_write(0xFD08142C, 0xFFFFFFFFU, 0x000C1800U); 1332 psu_mask_write(0xFD081430, 0xFFFFFFFFU, 0x71000000U); 1333 psu_mask_write(0xFD081440, 0xFFFFFFFFU, 0x2A019FFEU); 1334 psu_mask_write(0xFD081444, 0xFFFFFFFFU, 0x01100000U); 1335 psu_mask_write(0xFD08145C, 0xFFFFFFFFU, 0x01264300U); 1336 psu_mask_write(0xFD08146C, 0xFFFFFFFFU, 0x000C1800U); 1337 psu_mask_write(0xFD081470, 0xFFFFFFFFU, 0x71000000U); 1338 psu_mask_write(0xFD081480, 0xFFFFFFFFU, 0x15019FFEU); 1339 psu_mask_write(0xFD081484, 0xFFFFFFFFU, 0x21100000U); 1340 psu_mask_write(0xFD08149C, 0xFFFFFFFFU, 0x01266300U); 1341 psu_mask_write(0xFD0814AC, 0xFFFFFFFFU, 0x000C1800U); 1342 psu_mask_write(0xFD0814B0, 0xFFFFFFFFU, 0x70400000U); 1343 psu_mask_write(0xFD0814C0, 0xFFFFFFFFU, 0x15019FFEU); 1344 psu_mask_write(0xFD0814C4, 0xFFFFFFFFU, 0x21100000U); 1345 psu_mask_write(0xFD0814DC, 0xFFFFFFFFU, 0x01266300U); 1346 psu_mask_write(0xFD0814EC, 0xFFFFFFFFU, 0x000C1800U); 1347 psu_mask_write(0xFD0814F0, 0xFFFFFFFFU, 0x70400000U); 1348 psu_mask_write(0xFD081500, 0xFFFFFFFFU, 0x15019FFEU); 1349 psu_mask_write(0xFD081504, 0xFFFFFFFFU, 0x21100000U); 1350 psu_mask_write(0xFD08151C, 0xFFFFFFFFU, 0x01266300U); 1351 psu_mask_write(0xFD08152C, 0xFFFFFFFFU, 0x000C1800U); 1352 psu_mask_write(0xFD081530, 0xFFFFFFFFU, 0x70400000U); 1353 psu_mask_write(0xFD0817DC, 0xFFFFFFFFU, 0x012643C4U); 1354 1355 return 1; 1356} 1357 1358static unsigned long psu_ddr_qos_init_data(void) 1359{ 1360 psu_mask_write(0xFD360008, 0x0000000FU, 0x00000000U); 1361 psu_mask_write(0xFD36001C, 0x0000000FU, 0x00000000U); 1362 psu_mask_write(0xFD370008, 0x0000000FU, 0x00000000U); 1363 psu_mask_write(0xFD37001C, 0x0000000FU, 0x00000000U); 1364 psu_mask_write(0xFD380008, 0x0000000FU, 0x00000000U); 1365 psu_mask_write(0xFD38001C, 0x0000000FU, 0x00000000U); 1366 psu_mask_write(0xFD390008, 0x0000000FU, 0x00000000U); 1367 psu_mask_write(0xFD39001C, 0x0000000FU, 0x00000000U); 1368 psu_mask_write(0xFD3A0008, 0x0000000FU, 0x00000000U); 1369 psu_mask_write(0xFD3A001C, 0x0000000FU, 0x00000000U); 1370 psu_mask_write(0xFD3B0008, 0x0000000FU, 0x00000000U); 1371 psu_mask_write(0xFD3B001C, 0x0000000FU, 0x00000000U); 1372 psu_mask_write(0xFF9B0008, 0x0000000FU, 0x00000000U); 1373 psu_mask_write(0xFF9B001C, 0x0000000FU, 0x00000000U); 1374 1375 return 1; 1376} 1377 1378static unsigned long psu_mio_init_data(void) 1379{ 1380 psu_mask_write(0xFF180000, 0x000000FEU, 0x00000000U); 1381 psu_mask_write(0xFF180004, 0x000000FEU, 0x00000000U); 1382 psu_mask_write(0xFF180008, 0x000000FEU, 0x00000000U); 1383 psu_mask_write(0xFF18000C, 0x000000FEU, 0x00000000U); 1384 psu_mask_write(0xFF180010, 0x000000FEU, 0x00000000U); 1385 psu_mask_write(0xFF180014, 0x000000FEU, 0x00000000U); 1386 psu_mask_write(0xFF180018, 0x000000FEU, 0x00000000U); 1387 psu_mask_write(0xFF18001C, 0x000000FEU, 0x00000000U); 1388 psu_mask_write(0xFF180020, 0x000000FEU, 0x00000000U); 1389 psu_mask_write(0xFF180024, 0x000000FEU, 0x00000000U); 1390 psu_mask_write(0xFF180028, 0x000000FEU, 0x00000000U); 1391 psu_mask_write(0xFF18002C, 0x000000FEU, 0x00000000U); 1392 psu_mask_write(0xFF180030, 0x000000FEU, 0x00000000U); 1393 psu_mask_write(0xFF180034, 0x000000FEU, 0x00000000U); 1394 psu_mask_write(0xFF180038, 0x000000FEU, 0x00000000U); 1395 psu_mask_write(0xFF18003C, 0x000000FEU, 0x00000000U); 1396 psu_mask_write(0xFF180040, 0x000000FEU, 0x00000000U); 1397 psu_mask_write(0xFF180044, 0x000000FEU, 0x00000000U); 1398 psu_mask_write(0xFF180048, 0x000000FEU, 0x00000000U); 1399 psu_mask_write(0xFF18004C, 0x000000FEU, 0x00000000U); 1400 psu_mask_write(0xFF180050, 0x000000FEU, 0x00000000U); 1401 psu_mask_write(0xFF180054, 0x000000FEU, 0x00000000U); 1402 psu_mask_write(0xFF180058, 0x000000FEU, 0x00000000U); 1403 psu_mask_write(0xFF18005C, 0x000000FEU, 0x00000000U); 1404 psu_mask_write(0xFF180060, 0x000000FEU, 0x00000000U); 1405 psu_mask_write(0xFF180064, 0x000000FEU, 0x00000000U); 1406 psu_mask_write(0xFF180068, 0x000000FEU, 0x00000000U); 1407 psu_mask_write(0xFF18006C, 0x000000FEU, 0x00000000U); 1408 psu_mask_write(0xFF180070, 0x000000FEU, 0x00000000U); 1409 psu_mask_write(0xFF180074, 0x000000FEU, 0x00000000U); 1410 psu_mask_write(0xFF180078, 0x000000FEU, 0x00000000U); 1411 psu_mask_write(0xFF18007C, 0x000000FEU, 0x00000000U); 1412 psu_mask_write(0xFF180080, 0x000000FEU, 0x00000000U); 1413 psu_mask_write(0xFF180084, 0x000000FEU, 0x00000000U); 1414 psu_mask_write(0xFF180088, 0x000000FEU, 0x00000040U); 1415 psu_mask_write(0xFF18008C, 0x000000FEU, 0x00000040U); 1416 psu_mask_write(0xFF180090, 0x000000FEU, 0x00000040U); 1417 psu_mask_write(0xFF180094, 0x000000FEU, 0x00000040U); 1418 psu_mask_write(0xFF180098, 0x000000FEU, 0x000000C0U); 1419 psu_mask_write(0xFF18009C, 0x000000FEU, 0x000000C0U); 1420 psu_mask_write(0xFF1800A0, 0x000000FEU, 0x00000000U); 1421 psu_mask_write(0xFF1800A4, 0x000000FEU, 0x00000000U); 1422 psu_mask_write(0xFF1800A8, 0x000000FEU, 0x00000000U); 1423 psu_mask_write(0xFF1800AC, 0x000000FEU, 0x00000000U); 1424 psu_mask_write(0xFF1800B0, 0x000000FEU, 0x00000000U); 1425 psu_mask_write(0xFF1800B4, 0x000000FEU, 0x00000010U); 1426 psu_mask_write(0xFF1800B8, 0x000000FEU, 0x00000010U); 1427 psu_mask_write(0xFF1800BC, 0x000000FEU, 0x00000010U); 1428 psu_mask_write(0xFF1800C0, 0x000000FEU, 0x00000010U); 1429 psu_mask_write(0xFF1800C4, 0x000000FEU, 0x00000010U); 1430 psu_mask_write(0xFF1800C8, 0x000000FEU, 0x00000010U); 1431 psu_mask_write(0xFF1800CC, 0x000000FEU, 0x00000010U); 1432 psu_mask_write(0xFF1800D0, 0x000000FEU, 0x00000000U); 1433 psu_mask_write(0xFF1800D4, 0x000000FEU, 0x00000000U); 1434 psu_mask_write(0xFF1800D8, 0x000000FEU, 0x00000000U); 1435 psu_mask_write(0xFF1800DC, 0x000000FEU, 0x00000000U); 1436 psu_mask_write(0xFF1800E0, 0x000000FEU, 0x00000000U); 1437 psu_mask_write(0xFF1800E4, 0x000000FEU, 0x00000000U); 1438 psu_mask_write(0xFF1800E8, 0x000000FEU, 0x00000000U); 1439 psu_mask_write(0xFF1800EC, 0x000000FEU, 0x00000000U); 1440 psu_mask_write(0xFF1800F0, 0x000000FEU, 0x00000000U); 1441 psu_mask_write(0xFF1800F4, 0x000000FEU, 0x00000000U); 1442 psu_mask_write(0xFF1800F8, 0x000000FEU, 0x00000000U); 1443 psu_mask_write(0xFF1800FC, 0x000000FEU, 0x00000000U); 1444 psu_mask_write(0xFF180100, 0x000000FEU, 0x00000000U); 1445 psu_mask_write(0xFF180104, 0x000000FEU, 0x00000000U); 1446 psu_mask_write(0xFF180108, 0x000000FEU, 0x00000000U); 1447 psu_mask_write(0xFF18010C, 0x000000FEU, 0x00000000U); 1448 psu_mask_write(0xFF180110, 0x000000FEU, 0x00000000U); 1449 psu_mask_write(0xFF180114, 0x000000FEU, 0x00000000U); 1450 psu_mask_write(0xFF180118, 0x000000FEU, 0x00000000U); 1451 psu_mask_write(0xFF18011C, 0x000000FEU, 0x00000000U); 1452 psu_mask_write(0xFF180120, 0x000000FEU, 0x00000000U); 1453 psu_mask_write(0xFF180124, 0x000000FEU, 0x00000000U); 1454 psu_mask_write(0xFF180128, 0x000000FEU, 0x00000000U); 1455 psu_mask_write(0xFF18012C, 0x000000FEU, 0x00000000U); 1456 psu_mask_write(0xFF180130, 0x000000FEU, 0x00000060U); 1457 psu_mask_write(0xFF180134, 0x000000FEU, 0x00000060U); 1458 psu_mask_write(0xFF180204, 0xFFFFFFFFU, 0x00000000U); 1459 psu_mask_write(0xFF180208, 0xFFFFFFFFU, 0x00002040U); 1460 psu_mask_write(0xFF18020C, 0x00003FFFU, 0x00000000U); 1461 psu_mask_write(0xFF180138, 0x03FFFFFFU, 0x03FFFFFFU); 1462 psu_mask_write(0xFF18013C, 0x03FFFFFFU, 0x03FFFFFFU); 1463 psu_mask_write(0xFF180140, 0x03FFFFFFU, 0x00000000U); 1464 psu_mask_write(0xFF180144, 0x03FFFFFFU, 0x03FFFFFFU); 1465 psu_mask_write(0xFF180148, 0x03FFFFFFU, 0x03FFFFFFU); 1466 psu_mask_write(0xFF18014C, 0x03FFFFFFU, 0x00000000U); 1467 psu_mask_write(0xFF180154, 0x03FFFFFFU, 0x03FFFFFFU); 1468 psu_mask_write(0xFF180158, 0x03FFFFFFU, 0x03FFFFFFU); 1469 psu_mask_write(0xFF18015C, 0x03FFFFFFU, 0x00000000U); 1470 psu_mask_write(0xFF180160, 0x03FFFFFFU, 0x03FFFFFFU); 1471 psu_mask_write(0xFF180164, 0x03FFFFFFU, 0x03FFFFFFU); 1472 psu_mask_write(0xFF180168, 0x03FFFFFFU, 0x00000000U); 1473 psu_mask_write(0xFF180170, 0x03FFFFFFU, 0x03FFFFFFU); 1474 psu_mask_write(0xFF180174, 0x03FFFFFFU, 0x03FFFFFFU); 1475 psu_mask_write(0xFF180178, 0x03FFFFFFU, 0x00000000U); 1476 psu_mask_write(0xFF18017C, 0x03FFFFFFU, 0x03FFFFFFU); 1477 psu_mask_write(0xFF180180, 0x03FFFFFFU, 0x03FFFFFFU); 1478 psu_mask_write(0xFF180184, 0x03FFFFFFU, 0x00000000U); 1479 psu_mask_write(0xFF180200, 0x0000000FU, 0x00000000U); 1480 1481 return 1; 1482} 1483 1484static unsigned long psu_peripherals_pre_init_data(void) 1485{ 1486 psu_mask_write(0xFF5E0108, 0x013F3F07U, 0x01012302U); 1487 1488 return 1; 1489} 1490 1491static unsigned long psu_peripherals_init_data(void) 1492{ 1493 psu_mask_write(0xFD1A0100, 0x0000007CU, 0x00000000U); 1494 psu_mask_write(0xFF5E0238, 0x001A0000U, 0x00000000U); 1495 psu_mask_write(0xFF5E023C, 0x0093C018U, 0x00000000U); 1496 psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); 1497 psu_mask_write(0xFF5E0238, 0x00000040U, 0x00000000U); 1498 psu_mask_write(0xFF180310, 0x00008000U, 0x00000000U); 1499 psu_mask_write(0xFF180320, 0x33840000U, 0x00800000U); 1500 psu_mask_write(0xFF18031C, 0x7FFE0000U, 0x64500000U); 1501 psu_mask_write(0xFF180358, 0x00000008U, 0x00000008U); 1502 psu_mask_write(0xFF180324, 0x03C00000U, 0x00000000U); 1503 psu_mask_write(0xFF5E0238, 0x00000600U, 0x00000000U); 1504 psu_mask_write(0xFF5E0238, 0x00000002U, 0x00000000U); 1505 psu_mask_write(0xFF5E0238, 0x00040000U, 0x00000000U); 1506 psu_mask_write(0xFF4B0024, 0x000000FFU, 0x000000FFU); 1507 psu_mask_write(0xFFCA5000, 0x00001FFFU, 0x00000000U); 1508 psu_mask_write(0xFD5C0060, 0x000F000FU, 0x00000000U); 1509 psu_mask_write(0xFFA60040, 0x80000000U, 0x80000000U); 1510 psu_mask_write(0xFF260020, 0xFFFFFFFFU, 0x05F5DD18U); 1511 psu_mask_write(0xFF260000, 0x00000001U, 0x00000001U); 1512 return 1; 1513} 1514 1515static unsigned long psu_serdes_init_data(void) 1516{ 1517 psu_mask_write(0xFD410000, 0x0000001FU, 0x0000000FU); 1518 psu_mask_write(0xFD402860, 0x00000080U, 0x00000080U); 1519 psu_mask_write(0xFD40106C, 0x0000000FU, 0x0000000FU); 1520 psu_mask_write(0xFD4000F4, 0x0000000BU, 0x0000000BU); 1521 psu_mask_write(0xFD401074, 0x00000010U, 0x00000010U); 1522 psu_mask_write(0xFD405074, 0x00000010U, 0x00000010U); 1523 psu_mask_write(0xFD409074, 0x00000010U, 0x00000010U); 1524 psu_mask_write(0xFD40D074, 0x00000010U, 0x00000010U); 1525 psu_mask_write(0xFD40189C, 0x00000080U, 0x00000080U); 1526 psu_mask_write(0xFD4018F8, 0x000000FFU, 0x0000007DU); 1527 psu_mask_write(0xFD4018FC, 0x000000FFU, 0x0000007DU); 1528 psu_mask_write(0xFD401990, 0x000000FFU, 0x00000000U); 1529 psu_mask_write(0xFD401924, 0x000000FFU, 0x00000082U); 1530 psu_mask_write(0xFD401928, 0x000000FFU, 0x00000000U); 1531 psu_mask_write(0xFD401900, 0x000000FFU, 0x00000064U); 1532 psu_mask_write(0xFD40192C, 0x000000FFU, 0x00000000U); 1533 psu_mask_write(0xFD401980, 0x000000FFU, 0x000000FFU); 1534 psu_mask_write(0xFD401914, 0x000000FFU, 0x000000FFU); 1535 psu_mask_write(0xFD401918, 0x00000001U, 0x00000001U); 1536 psu_mask_write(0xFD401940, 0x000000FFU, 0x000000FFU); 1537 psu_mask_write(0xFD401944, 0x00000001U, 0x00000001U); 1538 psu_mask_write(0xFD401994, 0x00000007U, 0x00000007U); 1539 psu_mask_write(0xFD405994, 0x00000007U, 0x00000007U); 1540 psu_mask_write(0xFD409994, 0x00000007U, 0x00000007U); 1541 psu_mask_write(0xFD40D994, 0x00000007U, 0x00000007U); 1542 psu_mask_write(0xFD40107C, 0x0000000FU, 0x00000001U); 1543 psu_mask_write(0xFD40507C, 0x0000000FU, 0x00000001U); 1544 psu_mask_write(0xFD40907C, 0x0000000FU, 0x00000001U); 1545 psu_mask_write(0xFD40D07C, 0x0000000FU, 0x00000001U); 1546 psu_mask_write(0xFD4019A4, 0x000000FFU, 0x000000FFU); 1547 psu_mask_write(0xFD401038, 0x00000040U, 0x00000040U); 1548 psu_mask_write(0xFD40102C, 0x00000040U, 0x00000040U); 1549 psu_mask_write(0xFD4059A4, 0x000000FFU, 0x000000FFU); 1550 psu_mask_write(0xFD405038, 0x00000040U, 0x00000040U); 1551 psu_mask_write(0xFD40502C, 0x00000040U, 0x00000040U); 1552 psu_mask_write(0xFD4099A4, 0x000000FFU, 0x000000FFU); 1553 psu_mask_write(0xFD409038, 0x00000040U, 0x00000040U); 1554 psu_mask_write(0xFD40902C, 0x00000040U, 0x00000040U); 1555 psu_mask_write(0xFD40D9A4, 0x000000FFU, 0x000000FFU); 1556 psu_mask_write(0xFD40D038, 0x00000040U, 0x00000040U); 1557 psu_mask_write(0xFD40D02C, 0x00000040U, 0x00000040U); 1558 psu_mask_write(0xFD4019AC, 0x00000003U, 0x00000000U); 1559 psu_mask_write(0xFD4059AC, 0x00000003U, 0x00000000U); 1560 psu_mask_write(0xFD4099AC, 0x00000003U, 0x00000000U); 1561 psu_mask_write(0xFD40D9AC, 0x00000003U, 0x00000000U); 1562 psu_mask_write(0xFD401978, 0x00000010U, 0x00000010U); 1563 psu_mask_write(0xFD405978, 0x00000010U, 0x00000010U); 1564 psu_mask_write(0xFD409978, 0x00000010U, 0x00000010U); 1565 psu_mask_write(0xFD40D978, 0x00000010U, 0x00000010U); 1566 1567 serdes_illcalib(0, 0, 0, 0, 0, 0, 5, 0); 1568 psu_mask_write(0xFD410010, 0x00000007U, 0x00000005U); 1569 psu_mask_write(0xFD410040, 0x00000003U, 0x00000000U); 1570 psu_mask_write(0xFD410044, 0x00000003U, 0x00000000U); 1571 1572 return 1; 1573} 1574 1575static unsigned long psu_resetout_init_data(void) 1576{ 1577 psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000000U); 1578 psu_mask_write(0xFD480064, 0x00000200U, 0x00000200U); 1579 mask_poll(0xFD4023E4, 0x00000010U); 1580 1581 return 1; 1582} 1583 1584static unsigned long psu_resetin_init_data(void) 1585{ 1586 psu_mask_write(0xFF5E0230, 0x00000001U, 0x00000001U); 1587 1588 return 1; 1589} 1590 1591static unsigned long psu_afi_config(void) 1592{ 1593 psu_mask_write(0xFD1A0100, 0x00001F80U, 0x00000000U); 1594 psu_mask_write(0xFF5E023C, 0x00080000U, 0x00000000U); 1595 psu_mask_write(0xFF419000, 0x00000300U, 0x00000000U); 1596 1597 return 1; 1598} 1599 1600static unsigned long psu_ddr_phybringup_data(void) 1601{ 1602 unsigned int regval = 0; 1603 1604 for (int tp = 0; tp < 20; tp++) 1605 regval = Xil_In32(0xFD070018); 1606 int cur_PLLCR0; 1607 1608 cur_PLLCR0 = (Xil_In32(0xFD080068U) & 0xFFFFFFFFU) >> 0x00000000U; 1609 int cur_DX8SL0PLLCR0; 1610 1611 cur_DX8SL0PLLCR0 = (Xil_In32(0xFD081404U) & 0xFFFFFFFFU) >> 0x00000000U; 1612 int cur_DX8SL1PLLCR0; 1613 1614 cur_DX8SL1PLLCR0 = (Xil_In32(0xFD081444U) & 0xFFFFFFFFU) >> 0x00000000U; 1615 int cur_DX8SL2PLLCR0; 1616 1617 cur_DX8SL2PLLCR0 = (Xil_In32(0xFD081484U) & 0xFFFFFFFFU) >> 0x00000000U; 1618 int cur_DX8SL3PLLCR0; 1619 1620 cur_DX8SL3PLLCR0 = (Xil_In32(0xFD0814C4U) & 0xFFFFFFFFU) >> 0x00000000U; 1621 int cur_DX8SL4PLLCR0; 1622 1623 cur_DX8SL4PLLCR0 = (Xil_In32(0xFD081504U) & 0xFFFFFFFFU) >> 0x00000000U; 1624 int cur_DX8SLBPLLCR0; 1625 1626 cur_DX8SLBPLLCR0 = (Xil_In32(0xFD0817C4U) & 0xFFFFFFFFU) >> 0x00000000U; 1627 Xil_Out32(0xFD080068, 0x02120000); 1628 Xil_Out32(0xFD081404, 0x02120000); 1629 Xil_Out32(0xFD081444, 0x02120000); 1630 Xil_Out32(0xFD081484, 0x02120000); 1631 Xil_Out32(0xFD0814C4, 0x02120000); 1632 Xil_Out32(0xFD081504, 0x02120000); 1633 Xil_Out32(0xFD0817C4, 0x02120000); 1634 int cur_div2; 1635 1636 cur_div2 = (Xil_In32(0xFD1A002CU) & 0x00010000U) >> 0x00000010U; 1637 int cur_fbdiv; 1638 1639 cur_fbdiv = (Xil_In32(0xFD1A002CU) & 0x00007F00U) >> 0x00000008U; 1640 dpll_prog(1, 49, 63, 625, 3, 3, 2); 1641 for (int tp = 0; tp < 20; tp++) 1642 regval = Xil_In32(0xFD070018); 1643 unsigned int pll_retry = 10; 1644 unsigned int pll_locked = 0; 1645 1646 while ((pll_retry > 0) && (!pll_locked)) { 1647 Xil_Out32(0xFD080004, 0x00040010); 1648 Xil_Out32(0xFD080004, 0x00040011); 1649 1650 while ((Xil_In32(0xFD080030) & 0x1) != 1) 1651 ; 1652 pll_locked = (Xil_In32(0xFD080030) & 0x80000000) 1653 >> 31; 1654 pll_locked &= (Xil_In32(0xFD0807E0) & 0x10000) 1655 >> 16; 1656 pll_locked &= (Xil_In32(0xFD0809E0) & 0x10000) >> 16; 1657 pll_retry--; 1658 } 1659 Xil_Out32(0xFD0800C4, Xil_In32(0xFD0800C4) | (pll_retry << 16)); 1660 if (!pll_locked) 1661 return 0; 1662 1663 Xil_Out32(0xFD080004U, 0x00040063U); 1664 Xil_Out32(0xFD0800C0U, 0x00000001U); 1665 1666 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) 1667 ; 1668 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); 1669 1670 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) 1671 ; 1672 Xil_Out32(0xFD070010U, 0x80000018U); 1673 Xil_Out32(0xFD0701B0U, 0x00000005U); 1674 regval = Xil_In32(0xFD070018); 1675 while ((regval & 0x1) != 0x0) 1676 regval = Xil_In32(0xFD070018); 1677 1678 regval = Xil_In32(0xFD070018); 1679 regval = Xil_In32(0xFD070018); 1680 regval = Xil_In32(0xFD070018); 1681 regval = Xil_In32(0xFD070018); 1682 regval = Xil_In32(0xFD070018); 1683 regval = Xil_In32(0xFD070018); 1684 regval = Xil_In32(0xFD070018); 1685 regval = Xil_In32(0xFD070018); 1686 regval = Xil_In32(0xFD070018); 1687 regval = Xil_In32(0xFD070018); 1688 Xil_Out32(0xFD070014U, 0x00000331U); 1689 Xil_Out32(0xFD070010U, 0x80000018U); 1690 regval = Xil_In32(0xFD070018); 1691 while ((regval & 0x1) != 0x0) 1692 regval = Xil_In32(0xFD070018); 1693 1694 regval = Xil_In32(0xFD070018); 1695 regval = Xil_In32(0xFD070018); 1696 regval = Xil_In32(0xFD070018); 1697 regval = Xil_In32(0xFD070018); 1698 regval = Xil_In32(0xFD070018); 1699 regval = Xil_In32(0xFD070018); 1700 regval = Xil_In32(0xFD070018); 1701 regval = Xil_In32(0xFD070018); 1702 regval = Xil_In32(0xFD070018); 1703 regval = Xil_In32(0xFD070018); 1704 Xil_Out32(0xFD070014U, 0x00000B36U); 1705 Xil_Out32(0xFD070010U, 0x80000018U); 1706 regval = Xil_In32(0xFD070018); 1707 while ((regval & 0x1) != 0x0) 1708 regval = Xil_In32(0xFD070018); 1709 1710 regval = Xil_In32(0xFD070018); 1711 regval = Xil_In32(0xFD070018); 1712 regval = Xil_In32(0xFD070018); 1713 regval = Xil_In32(0xFD070018); 1714 regval = Xil_In32(0xFD070018); 1715 regval = Xil_In32(0xFD070018); 1716 regval = Xil_In32(0xFD070018); 1717 regval = Xil_In32(0xFD070018); 1718 regval = Xil_In32(0xFD070018); 1719 regval = Xil_In32(0xFD070018); 1720 Xil_Out32(0xFD070014U, 0x00000C56U); 1721 Xil_Out32(0xFD070010U, 0x80000018U); 1722 regval = Xil_In32(0xFD070018); 1723 while ((regval & 0x1) != 0x0) 1724 regval = Xil_In32(0xFD070018); 1725 1726 regval = Xil_In32(0xFD070018); 1727 regval = Xil_In32(0xFD070018); 1728 regval = Xil_In32(0xFD070018); 1729 regval = Xil_In32(0xFD070018); 1730 regval = Xil_In32(0xFD070018); 1731 regval = Xil_In32(0xFD070018); 1732 regval = Xil_In32(0xFD070018); 1733 regval = Xil_In32(0xFD070018); 1734 regval = Xil_In32(0xFD070018); 1735 regval = Xil_In32(0xFD070018); 1736 Xil_Out32(0xFD070014U, 0x00000E19U); 1737 Xil_Out32(0xFD070010U, 0x80000018U); 1738 regval = Xil_In32(0xFD070018); 1739 while ((regval & 0x1) != 0x0) 1740 regval = Xil_In32(0xFD070018); 1741 1742 regval = Xil_In32(0xFD070018); 1743 regval = Xil_In32(0xFD070018); 1744 regval = Xil_In32(0xFD070018); 1745 regval = Xil_In32(0xFD070018); 1746 regval = Xil_In32(0xFD070018); 1747 regval = Xil_In32(0xFD070018); 1748 regval = Xil_In32(0xFD070018); 1749 regval = Xil_In32(0xFD070018); 1750 regval = Xil_In32(0xFD070018); 1751 regval = Xil_In32(0xFD070018); 1752 Xil_Out32(0xFD070014U, 0x00001616U); 1753 Xil_Out32(0xFD070010U, 0x80000018U); 1754 Xil_Out32(0xFD070010U, 0x80000010U); 1755 Xil_Out32(0xFD0701B0U, 0x00000005U); 1756 Xil_Out32(0xFD070320U, 0x00000001U); 1757 while ((Xil_In32(0xFD070004U) & 0x0000000FU) != 0x00000001U) 1758 ; 1759 prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000000U); 1760 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); 1761 prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000001U); 1762 prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000001U); 1763 prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); 1764 prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); 1765 prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000002U); 1766 prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); 1767 for (int tp = 0; tp < 20; tp++) 1768 regval = Xil_In32(0xFD070018); 1769 1770 Xil_Out32(0xFD080068, cur_PLLCR0); 1771 Xil_Out32(0xFD081404, cur_DX8SL0PLLCR0); 1772 Xil_Out32(0xFD081444, cur_DX8SL1PLLCR0); 1773 Xil_Out32(0xFD081484, cur_DX8SL2PLLCR0); 1774 Xil_Out32(0xFD0814C4, cur_DX8SL3PLLCR0); 1775 Xil_Out32(0xFD081504, cur_DX8SL4PLLCR0); 1776 Xil_Out32(0xFD0817C4, cur_DX8SLBPLLCR0); 1777 for (int tp = 0; tp < 20; tp++) 1778 regval = Xil_In32(0xFD070018); 1779 1780 dpll_prog(cur_div2, cur_fbdiv, 63, 625, 3, 3, 2); 1781 for (int tp = 0; tp < 2000; tp++) 1782 regval = Xil_In32(0xFD070018); 1783 1784 prog_reg(0xFD080004U, 0x20000000U, 0x0000001DU, 0x00000000U); 1785 prog_reg(0xFD080004U, 0x00040000U, 0x00000012U, 0x00000001U); 1786 prog_reg(0xFD080004U, 0x00000040U, 0x00000006U, 0x00000001U); 1787 prog_reg(0xFD080004U, 0x00000020U, 0x00000005U, 0x00000001U); 1788 prog_reg(0xFD080004U, 0x00000010U, 0x00000004U, 0x00000001U); 1789 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); 1790 1791 while ((Xil_In32(0xFD080030U) & 0x0000000FU) != 0x0000000FU) 1792 ; 1793 prog_reg(0xFD080004U, 0x00000001U, 0x00000000U, 0x00000001U); 1794 1795 while ((Xil_In32(0xFD080030U) & 0x000000FFU) != 0x0000001FU) 1796 ; 1797 for (int tp = 0; tp < 2000; tp++) 1798 regval = Xil_In32(0xFD070018); 1799 1800 prog_reg(0xFD080028U, 0x00000001U, 0x00000000U, 0x00000000U); 1801 prog_reg(0xFD08016CU, 0x00000004U, 0x00000002U, 0x00000001U); 1802 prog_reg(0xFD080168U, 0x000000F0U, 0x00000004U, 0x00000007U); 1803 prog_reg(0xFD080168U, 0x00000F00U, 0x00000008U, 0x00000003U); 1804 prog_reg(0xFD080168U, 0x0000000FU, 0x00000000U, 0x00000001U); 1805 for (int tp = 0; tp < 2000; tp++) 1806 regval = Xil_In32(0xFD070018); 1807 1808 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000001U); 1809 Xil_Out32(0xFD080004, 0x0014FE01); 1810 1811 regval = Xil_In32(0xFD080030); 1812 while (regval != 0x8000007E) 1813 regval = Xil_In32(0xFD080030); 1814 1815 Xil_Out32(0xFD080200U, 0x000091C7U); 1816 regval = Xil_In32(0xFD080030); 1817 while (regval != 0x80008FFF) 1818 regval = Xil_In32(0xFD080030); 1819 1820 Xil_Out32(0xFD080200U, 0x800091C7U); 1821 regval = ((Xil_In32(0xFD080030) & 0x1FFF0000) >> 18); 1822 if (regval != 0) 1823 return 0; 1824 prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000000U); 1825 prog_reg(0xFD0701B0U, 0x00000001U, 0x00000000U, 0x00000001U); 1826 prog_reg(0xFD0701A0U, 0x80000000U, 0x0000001FU, 0x00000000U); 1827 prog_reg(0xFD070320U, 0x00000001U, 0x00000000U, 0x00000001U); 1828 Xil_Out32(0xFD070180U, 0x02160010U); 1829 Xil_Out32(0xFD070060U, 0x00000000U); 1830 prog_reg(0xFD080014U, 0x00000040U, 0x00000006U, 0x00000000U); 1831 for (int tp = 0; tp < 4000; tp++) 1832 regval = Xil_In32(0xFD070018); 1833 1834 prog_reg(0xFD080090U, 0x00000FC0U, 0x00000006U, 0x00000007U); 1835 prog_reg(0xFD080090U, 0x00000004U, 0x00000002U, 0x00000001U); 1836 prog_reg(0xFD08070CU, 0x02000000U, 0x00000019U, 0x00000000U); 1837 prog_reg(0xFD08080CU, 0x02000000U, 0x00000019U, 0x00000000U); 1838 prog_reg(0xFD08090CU, 0x02000000U, 0x00000019U, 0x00000000U); 1839 prog_reg(0xFD080A0CU, 0x02000000U, 0x00000019U, 0x00000000U); 1840 prog_reg(0xFD080F0CU, 0x02000000U, 0x00000019U, 0x00000000U); 1841 prog_reg(0xFD080200U, 0x00000010U, 0x00000004U, 0x00000001U); 1842 prog_reg(0xFD080250U, 0x00000002U, 0x00000001U, 0x00000000U); 1843 prog_reg(0xFD080250U, 0x0000000CU, 0x00000002U, 0x00000001U); 1844 prog_reg(0xFD080250U, 0x000000F0U, 0x00000004U, 0x00000000U); 1845 prog_reg(0xFD080250U, 0x00300000U, 0x00000014U, 0x00000001U); 1846 prog_reg(0xFD080250U, 0xF0000000U, 0x0000001CU, 0x00000002U); 1847 prog_reg(0xFD08070CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1848 prog_reg(0xFD08080CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1849 prog_reg(0xFD08090CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1850 prog_reg(0xFD080A0CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1851 prog_reg(0xFD080B0CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1852 prog_reg(0xFD080C0CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1853 prog_reg(0xFD080D0CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1854 prog_reg(0xFD080E0CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1855 prog_reg(0xFD080F0CU, 0x08000000U, 0x0000001BU, 0x00000000U); 1856 prog_reg(0xFD080254U, 0x000000FFU, 0x00000000U, 0x00000001U); 1857 prog_reg(0xFD080254U, 0x000F0000U, 0x00000010U, 0x0000000AU); 1858 prog_reg(0xFD080250U, 0x00000001U, 0x00000000U, 0x00000001U); 1859 1860 return 1; 1861} 1862 1863static int serdes_enb_coarse_saturation(void) 1864{ 1865 Xil_Out32(0xFD402094, 0x00000010); 1866 Xil_Out32(0xFD406094, 0x00000010); 1867 Xil_Out32(0xFD40A094, 0x00000010); 1868 Xil_Out32(0xFD40E094, 0x00000010); 1869 return 1; 1870} 1871 1872static int serdes_fixcal_code(void) 1873{ 1874 int maskstatus = 1; 1875 unsigned int rdata = 0; 1876 unsigned int match_pmos_code[23]; 1877 unsigned int match_nmos_code[23]; 1878 unsigned int match_ical_code[7]; 1879 unsigned int match_rcal_code[7]; 1880 unsigned int p_code = 0; 1881 unsigned int n_code = 0; 1882 unsigned int i_code = 0; 1883 unsigned int r_code = 0; 1884 unsigned int repeat_count = 0; 1885 unsigned int L3_TM_CALIB_DIG20 = 0; 1886 unsigned int L3_TM_CALIB_DIG19 = 0; 1887 unsigned int L3_TM_CALIB_DIG18 = 0; 1888 unsigned int L3_TM_CALIB_DIG16 = 0; 1889 unsigned int L3_TM_CALIB_DIG15 = 0; 1890 unsigned int L3_TM_CALIB_DIG14 = 0; 1891 int i = 0; 1892 int count = 0; 1893 1894 rdata = Xil_In32(0xFD40289C); 1895 rdata = rdata & ~0x03; 1896 rdata = rdata | 0x1; 1897 Xil_Out32(0xFD40289C, rdata); 1898 1899 do { 1900 if (count == 1100000) 1901 break; 1902 rdata = Xil_In32(0xFD402B1C); 1903 count++; 1904 } while ((rdata & 0x0000000E) != 0x0000000E); 1905 1906 for (i = 0; i < 23; i++) { 1907 match_pmos_code[i] = 0; 1908 match_nmos_code[i] = 0; 1909 } 1910 for (i = 0; i < 7; i++) { 1911 match_ical_code[i] = 0; 1912 match_rcal_code[i] = 0; 1913 } 1914 1915 do { 1916 Xil_Out32(0xFD410010, 0x00000000); 1917 Xil_Out32(0xFD410014, 0x00000000); 1918 1919 Xil_Out32(0xFD410010, 0x00000001); 1920 Xil_Out32(0xFD410014, 0x00000000); 1921 1922 maskstatus = mask_poll(0xFD40EF14, 0x2); 1923 if (maskstatus == 0) { 1924 xil_printf("#SERDES initialization timed out\n\r"); 1925 return maskstatus; 1926 } 1927 1928 p_code = mask_read(0xFD40EF18, 0xFFFFFFFF); 1929 n_code = mask_read(0xFD40EF1C, 0xFFFFFFFF); 1930 ; 1931 i_code = mask_read(0xFD40EF24, 0xFFFFFFFF); 1932 r_code = mask_read(0xFD40EF28, 0xFFFFFFFF); 1933 ; 1934 1935 if (p_code >= 0x26 && p_code <= 0x3C) 1936 match_pmos_code[p_code - 0x26] += 1; 1937 1938 if (n_code >= 0x26 && n_code <= 0x3C) 1939 match_nmos_code[n_code - 0x26] += 1; 1940 1941 if (i_code >= 0xC && i_code <= 0x12) 1942 match_ical_code[i_code - 0xc] += 1; 1943 1944 if (r_code >= 0x6 && r_code <= 0xC) 1945 match_rcal_code[r_code - 0x6] += 1; 1946 1947 } while (repeat_count++ < 10); 1948 1949 for (i = 0; i < 23; i++) { 1950 if (match_pmos_code[i] >= match_pmos_code[0]) { 1951 match_pmos_code[0] = match_pmos_code[i]; 1952 p_code = 0x26 + i; 1953 } 1954 if (match_nmos_code[i] >= match_nmos_code[0]) { 1955 match_nmos_code[0] = match_nmos_code[i]; 1956 n_code = 0x26 + i; 1957 } 1958 } 1959 1960 for (i = 0; i < 7; i++) { 1961 if (match_ical_code[i] >= match_ical_code[0]) { 1962 match_ical_code[0] = match_ical_code[i]; 1963 i_code = 0xC + i; 1964 } 1965 if (match_rcal_code[i] >= match_rcal_code[0]) { 1966 match_rcal_code[0] = match_rcal_code[i]; 1967 r_code = 0x6 + i; 1968 } 1969 } 1970 1971 L3_TM_CALIB_DIG20 = mask_read(0xFD40EC50, 0xFFFFFFF0); 1972 L3_TM_CALIB_DIG20 = L3_TM_CALIB_DIG20 | 0x8 | ((p_code >> 2) & 0x7); 1973 1974 L3_TM_CALIB_DIG19 = mask_read(0xFD40EC4C, 0xFFFFFF18); 1975 L3_TM_CALIB_DIG19 = L3_TM_CALIB_DIG19 | ((p_code & 0x3) << 6) 1976 | 0x20 | 0x4 | ((n_code >> 3) & 0x3); 1977 1978 L3_TM_CALIB_DIG18 = mask_read(0xFD40EC48, 0xFFFFFF0F); 1979 L3_TM_CALIB_DIG18 = L3_TM_CALIB_DIG18 | ((n_code & 0x7) << 5) | 0x10; 1980 1981 L3_TM_CALIB_DIG16 = mask_read(0xFD40EC40, 0xFFFFFFF8); 1982 L3_TM_CALIB_DIG16 = L3_TM_CALIB_DIG16 | ((r_code >> 1) & 0x7); 1983 1984 L3_TM_CALIB_DIG15 = mask_read(0xFD40EC3C, 0xFFFFFF30); 1985 L3_TM_CALIB_DIG15 = L3_TM_CALIB_DIG15 | ((r_code & 0x1) << 7) 1986 | 0x40 | 0x8 | ((i_code >> 1) & 0x7); 1987 1988 L3_TM_CALIB_DIG14 = mask_read(0xFD40EC38, 0xFFFFFF3F); 1989 L3_TM_CALIB_DIG14 = L3_TM_CALIB_DIG14 | ((i_code & 0x1) << 7) | 0x40; 1990 1991 Xil_Out32(0xFD40EC50, L3_TM_CALIB_DIG20); 1992 Xil_Out32(0xFD40EC4C, L3_TM_CALIB_DIG19); 1993 Xil_Out32(0xFD40EC48, L3_TM_CALIB_DIG18); 1994 Xil_Out32(0xFD40EC40, L3_TM_CALIB_DIG16); 1995 Xil_Out32(0xFD40EC3C, L3_TM_CALIB_DIG15); 1996 Xil_Out32(0xFD40EC38, L3_TM_CALIB_DIG14); 1997 return maskstatus; 1998} 1999 2000static int init_serdes(void) 2001{ 2002 int status = 1; 2003 2004 status &= psu_resetin_init_data(); 2005 2006 status &= serdes_fixcal_code(); 2007 status &= serdes_enb_coarse_saturation(); 2008 2009 status &= psu_serdes_init_data(); 2010 status &= psu_resetout_init_data(); 2011 2012 return status; 2013} 2014 2015static void init_peripheral(void) 2016{ 2017 psu_mask_write(0xFD5F0018, 0x8000001FU, 0x8000001FU); 2018} 2019 2020int psu_init(void) 2021{ 2022 int status = 1; 2023 2024 status &= psu_mio_init_data(); 2025 status &= psu_peripherals_pre_init_data(); 2026 status &= psu_pll_init_data(); 2027 status &= psu_clock_init_data(); 2028 status &= psu_ddr_init_data(); 2029 status &= psu_ddr_phybringup_data(); 2030 status &= psu_peripherals_init_data(); 2031 status &= init_serdes(); 2032 init_peripheral(); 2033 2034 status &= psu_afi_config(); 2035 psu_ddr_qos_init_data(); 2036 2037 if (status == 0) 2038 return 1; 2039 return 0; 2040} 2041