| /u-boot/arch/sh/lib/ |
| H A D | udivsi3.S | 15 div1 r5,r4
17 div1 r5,r4; div1 r5,r4; div1 r5,r4
18 div1 r5,r4; div1 r5,r4; div1 r5,r4; rts; div1 r5,r4
21 div1 r5,r4; rotcl r0
22 div1 r
[all...] |
| H A D | udivsi3_i4i-Os.S | 38 div1 r5,r4
40 div1 r5,r4
41 div1 r5,r4
43 div1 r5,r4
48 div1 r5,r4
50 div1 r5,r4
58 div1 r5,r4
60 div1 r5,r4; div1 r5,r4; div1 r
[all...] |
| H A D | udivsi3_i4i.S | 23 div1 with case distinction for larger divisors in three more ranges.
54 div1 r5,r0
56 div1 r5,r0
57 div1 r5,r0
59 div1 r5,r0
101 div1 r5,r0
108 div1 r5,r0
111 div1 r5,r0
114 div1 r5,r0
117 div1 r
[all...] |
| H A D | udiv_qrnnd.S | 28 div1 r6,r0
|
| /u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clock.h | 29 unsigned int div1; member in struct:s5pc100_clock
65 unsigned int div1; member in struct:s5pc110_clock
|
| /u-boot/drivers/clk/imx/ |
| H A D | clk-composite-8m.c | 62 int div1, div2; local
69 for (div1 = 1; div1 <= PCG_PREDIV_MAX; div1++) {
71 int new_error = ((parent_rate / div1) / div2) - rate;
74 *prediv = div1;
|
| /u-boot/arch/arm/mach-sunxi/ |
| H A D | clock_sun8i_a83t.c | 110 unsigned int div1 = 0, div2 = 0; local
112 /* A83T PLL5 DDR rate = 24000000 * (n+1)/(div1+1)/(div2+1) */
116 div1 << CCM_PLL5_DIV1_SHIFT, &ccm->pll5_cfg);
129 int div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >> local
133 return 24000000 * n / div1 / div2;
|
| H A D | clock_sun50i_h6.c | 145 int div1, m; local
148 div1 = ((rval & CCM_PLL6_CTRL_P0_MASK) >>
152 div1 = ((rval & CCM_PLL6_CTRL_DIV1_MASK) >>
160 return 24000000U * n / m / div1 / div2;
|
| /u-boot/board/samsung/smdkc100/ |
| H A D | onenand.c | 40 value = readl(&clk->div1);
43 writel(value, &clk->div1);
|
| /u-boot/drivers/clk/ |
| H A D | clk_zynq.c | 230 u32 clk_ctrl, div0, div1; local
235 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
238 zynq_clk_get_pll_rate(priv, ddrpll_clk), div0), div1);
247 u32 div1 = 1; local
257 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
258 if (!div1)
259 div1 = 1;
269 div1);
292 u32 *div0, u32 *div1)
306 *div1
290 zynq_clk_calc_peripheral_two_divs(ulong rate, ulong pll_rate, u32 *div0, u32 *div1) argument
321 u32 clk_ctrl, div0 = 0, div1 = 0; local
[all...] |
| H A D | clk_zynqmp.c | 481 u32 div1 = 1; local
496 div1 = (clk_ctrl & CLK_CTRL_DIV1_MASK) >> CLK_CTRL_DIV1_SHIFT;
497 if (!div1)
498 div1 = 1;
513 DIV_ROUND_CLOSEST(pllrate, div0), div1);
521 u32 div1 = 1; local
579 div1 = (clk_ctrl & CLK_CTRL_DIV0_MASK) >> CLK_CTRL_DIV0_SHIFT;
580 if (!div1)
581 div1 = 1;
593 DIV_ROUND_CLOSEST(pllrate, div0), div1);
596 zynqmp_clk_calc_peripheral_two_divs(ulong rate, ulong pll_rate, u32 *div0, u32 *div1) argument
627 u32 clk_ctrl, div0 = 0, div1 = 0; local
[all...] |
| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock_defs.h | 24 u32 div1; /* 18 */ member in struct:pllctl_regs
|
| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | clock_sun50i_h6.h | 245 #define CCM_PLL5_CTRL_DIV1(div1) ((div1) << 0)
|
| /u-boot/arch/arm/mach-keystone/ |
| H A D | clock.c | 130 offset = pllctl_reg(data->pll, div1) + i;
|