1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2008-2009 Samsung Electronics
4 * Kyungmin Park <kyungmin.park@samsung.com>
5 */
6
7#include <common.h>
8#include <linux/compat.h>
9#include <linux/mtd/mtd.h>
10#include <linux/mtd/onenand.h>
11#include <linux/mtd/samsung_onenand.h>
12
13#include <onenand_uboot.h>
14
15#include <asm/io.h>
16#include <asm/arch/clock.h>
17
18int onenand_board_init(struct mtd_info *mtd)
19{
20	struct onenand_chip *this = mtd->priv;
21	struct s5pc100_clock *clk =
22			(struct s5pc100_clock *)samsung_get_base_clock();
23	struct samsung_onenand *onenand;
24	int value;
25
26	this->base = (void *)S5PC100_ONENAND_BASE;
27	onenand = (struct samsung_onenand *)this->base;
28
29	/* D0 Domain memory clock gating */
30	value = readl(&clk->gate_d01);
31	value &= ~(1 << 2);		/* CLK_ONENANDC */
32	value |= (1 << 2);
33	writel(value, &clk->gate_d01);
34
35	value = readl(&clk->src0);
36	value &= ~(1 << 24);		/* MUX_1nand: 0 from HCLKD0 */
37	value &= ~(1 << 20);		/* MUX_HREF: 0 from FIN_27M */
38	writel(value, &clk->src0);
39
40	value = readl(&clk->div1);
41	value &= ~(3 << 16);		/* PCLKD1_RATIO */
42	value |= (1 << 16);
43	writel(value, &clk->div1);
44
45	writel(ONENAND_MEM_RESET_COLD, &onenand->mem_reset);
46
47	while (!(readl(&onenand->int_err_stat) & RST_CMP))
48		continue;
49
50	writel(RST_CMP, &onenand->int_err_ack);
51
52	/*
53	 * Access_Clock [2:0]
54	 * 166 MHz, 134 Mhz : 3
55	 * 100 Mhz, 60 Mhz  : 2
56	 */
57	writel(0x3, &onenand->acc_clock);
58
59	writel(INT_ERR_ALL, &onenand->int_err_mask);
60	writel(1 << 0, &onenand->int_pin_en);	/* Enable */
61
62	value = readl(&onenand->int_err_mask);
63	value &= ~RDY_ACT;
64	writel(value, &onenand->int_err_mask);
65
66	s3c_onenand_init(mtd);
67
68	return 0;
69}
70