/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_ip_centralization.h | 9 int ddr3_tip_centralization_tx(u32 dev_num); 10 int ddr3_tip_centralization_rx(u32 dev_num); 11 int ddr3_tip_print_centralization_result(u32 dev_num); 12 int ddr3_tip_special_rx(u32 dev_num);
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H A D | mv_ddr4_training_leveling.h | 9 int mv_ddr4_dynamic_wl_supp(u32 dev_num);
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H A D | ddr3_training_hw_algo.h | 9 int ddr3_tip_vref(u32 dev_num); 10 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id); 11 int ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap);
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H A D | mv_ddr4_training.h | 12 int mv_ddr4_sdram_config(u32 dev_num); 15 int mv_ddr4_phy_config(u32 dev_num); 21 int mv_ddr4_calibration_adjust(u32 dev_num, u8 vref_en, u8 pod_only); 27 int mv_ddr4_calibration_validate(u32 dev_num);
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H A D | ddr3_training_leveling.h | 11 int ddr3_tip_print_wl_supp_result(u32 dev_num); 12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
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H A D | ddr_training_ip_db.h | 11 u32 pattern_table_get_word(u32 dev_num, enum hws_pattern type, u8 index);
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H A D | ddr3_training_ip_prv_if.h | 23 typedef int (*HWS_TIP_DUNIT_MUX_SELECT_FUNC_PTR)(u8 dev_num, int enable); 25 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 28 u8 dev_num, enum hws_access_type interface_access, u32 if_id, 31 u8 dev_num, enum mv_ddr_freq freq, 34 u8 dev_num, struct ddr3_device_info *info_ptr); 36 u8 dev_num, u32 cs_mask, struct hws_cs_config_info *cs_info); 38 u8 dev_num, u32 if_id, enum mv_ddr_freq freq); 39 typedef int (*HWS_GET_INIT_FREQ)(u8 dev_num, enum mv_ddr_freq *freq); 41 u32 dev_num, enum hws_access_type access_type, u32 dunit_id, 44 u32 dev_num, enu [all...] |
H A D | ddr3_training_ip_flow.h | 67 int ddr3_tip_write_leveling_static_config(u32 dev_num, u32 if_id, 70 int ddr3_tip_read_leveling_static_config(u32 dev_num, u32 if_id, 73 int ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, 75 int ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, 78 int ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, 80 int ddr3_tip_bus_read_modify_write(u32 dev_num, 85 int ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, 88 int ddr3_tip_bus_write(u32 dev_num, enum hws_access_type e_interface_access, 92 int ddr3_tip_freq_set(u32 dev_num, enum hws_access_type e_access, u32 if_id, 94 int ddr3_tip_adjust_dqs(u32 dev_num); [all...] |
H A D | ddr3_training_ip_pbs.h | 36 int ddr3_tip_pbs_rx(u32 dev_num); 37 int ddr3_tip_print_all_pbs_result(u32 dev_num); 38 int ddr3_tip_pbs_tx(u32 dev_num);
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H A D | mv_ddr4_mpr_pda_if.h | 38 int mv_ddr4_mode_regs_init(u8 dev_num); 39 int mv_ddr4_mpr_read(u8 dev_num, u32 mpr_num, u32 page_num, 43 int mv_ddr4_mpr_write(u8 dev_num, u32 mpr_location, u32 mpr_num, 45 int mv_ddr4_dq_pins_mapping(u8 dev_num); 46 int mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id, 49 int mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id, 53 int mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type, 55 int mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type, 57 int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
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H A D | ddr3_training_ip_bist.h | 35 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id, 37 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, 44 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, 46 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, 48 int ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num, 50 int ddr3_tip_print_regs(u32 dev_num); 51 int ddr3_tip_reg_dump(u32 dev_num); 52 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
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H A D | mv_ddr4_training_calibration.h | 18 int mv_ddr4_dq_vref_calibration(u8 dev_num, u16 (*pbs_tap_factor)[MAX_BUS_NUM][BUS_WIDTH_IN_BITS]); 21 int mv_ddr4_receiver_calibration(u8 dev_num);
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H A D | mv_ddr4_training.c | 20 static int a39x_z1_config(u32 dev_num); 37 int mv_ddr4_sdram_config(u32 dev_num) argument 51 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, SDRAM_CFG_REG, 57 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_PINS_MUX_REG, 66 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_DLL_TIMING_REG, 72 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_INIT_TIMIMG_REG, 78 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_TIMING_REG, 84 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, DRAM_ZQ_TIMING_REG, 93 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, if_id, SDRAM_CFG_REG, 99 a39x_z1_config(dev_num); 201 mv_ddr4_phy_config(u32 dev_num) argument 293 mv_ddr4_calibration_adjust(u32 dev_num, u8 vref_en, u8 pod_only) argument 468 a39x_z1_config(u32 dev_num) argument 493 mv_ddr4_training_main_flow(u32 dev_num) argument [all...] |
H A D | ddr3_training.c | 100 static int ddr3_tip_ddr3_training_main_flow(u32 dev_num); 101 static int ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, 103 static int ddr3_tip_ddr3_auto_tune(u32 dev_num); 106 static int odt_test(u32 dev_num, enum hws_algo_type algo_type); 109 int adll_calibration(u32 dev_num, enum hws_access_type access_type, 111 static int ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, 114 static int ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type, 249 static int ddr3_tip_rank_control(u32 dev_num, u32 if_id); 254 int ddr3_tip_tune_training_params(u32 dev_num, argument 300 int ddr3_tip_configure_cs(u32 dev_num, u3 argument 362 hws_ddr3_tip_init_controller(u32 dev_num, struct init_cntr_param *init_cntr_prm) argument 708 ddr3_tip_rev2_rank_control(u32 dev_num, u32 if_id) argument 762 ddr3_tip_rev3_rank_control(u32 dev_num, u32 if_id) argument 795 ddr3_tip_rank_control(u32 dev_num, u32 if_id) argument 830 ddr3_tip_validate_algo_components(u8 dev_num) argument 935 hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type) argument 974 odt_test(u32 dev_num, enum hws_algo_type algo_type) argument 1014 hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable) argument 1023 ddr3_tip_if_write(u32 dev_num, enum hws_access_type interface_access, u32 if_id, u32 reg_addr, u32 data_value, u32 mask) argument 1034 ddr3_tip_if_read(u32 dev_num, enum hws_access_type interface_access, u32 if_id, u32 reg_addr, u32 *data, u32 mask) argument 1045 ddr3_tip_if_polling(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 exp_value, u32 mask, u32 offset, u32 poll_tries) argument 1097 ddr3_tip_bus_read(u32 dev_num, u32 if_id, enum hws_access_type phy_access, u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 *data) argument 1108 ddr3_tip_bus_write(u32 dev_num, enum hws_access_type interface_access, u32 if_id, enum hws_access_type phy_access, u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 data_value) argument 1121 ddr3_tip_bus_read_modify_write(u32 dev_num, enum hws_access_type access_type, u32 interface_id, u32 phy_id, enum hws_ddr_phy phy_type, u32 reg_addr, u32 data_value, u32 reg_mask) argument 1155 adll_calibration(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1228 ddr3_tip_freq_set(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1646 ddr3_tip_write_odt(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 cl_value, u32 cwl_value) argument 1679 ddr3_tip_set_timing(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1829 ddr4_tip_set_timing(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum mv_ddr_freq frequency) argument 1889 ddr3_tip_write_cs_result(u32 dev_num, u32 offset) argument 1929 ddr3_tip_write_mrs_cmd(u32 dev_num, u32 *cs_mask_arr, enum mr_number mr_num, u32 data, u32 mask) argument 1960 ddr3_tip_reset_fifo_ptr(u32 dev_num) argument 1999 ddr3_tip_ddr3_reset_phy_regs(u32 dev_num) argument 2071 ddr3_tip_restore_dunit_regs(u32 dev_num) argument 2101 ddr3_tip_adll_regs_bypass(u32 dev_num, u32 reg_val1, u32 reg_val2) argument 2128 ddr3_tip_ddr3_training_main_flow(u32 dev_num) argument 2602 ddr3_tip_ddr3_auto_tune(u32 dev_num) argument 2671 ddr3_tip_enable_init_sequence(u32 dev_num) argument 2717 ddr3_tip_register_dq_table(u32 dev_num, u32 *table) argument [all...] |
H A D | ddr3_training_leveling.c | 22 static int ddr3_tip_dynamic_write_leveling_seq(u32 dev_num); 23 static int ddr3_tip_dynamic_read_leveling_seq(u32 dev_num); 24 static int ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num); 25 static int ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, 27 static int ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, 37 int ddr3_tip_dynamic_read_leveling(u32 dev_num, u32 freq) argument 50 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); 65 (dev_num, ACCESS_TYPE_UNICAST, if_id, 70 (dev_num, ACCESS_TYPE_UNICAST, if_id, 74 ddr3_tip_reset_fifo_ptr(dev_num); 315 ddr3_tip_legacy_dynamic_write_leveling(u32 dev_num) argument 356 ddr3_tip_legacy_dynamic_read_leveling(u32 dev_num) argument 397 ddr3_tip_dynamic_per_bit_read_leveling(u32 dev_num, u32 freq) argument 764 ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, u32 *cs_mask) argument 805 ddr3_tip_dynamic_write_leveling(u32 dev_num, int phase_remove) argument 1172 ddr3_tip_dynamic_write_leveling_supp(u32 dev_num) argument 1285 ddr3_tip_wl_supp_align_phase_shift(u32 dev_num, u32 if_id, u32 bus_id) argument 1365 ddr3_tip_xsb_compare_test(u32 dev_num, u32 if_id, u32 bus_id, u32 edge_offset) argument 1458 ddr3_tip_dynamic_write_leveling_seq(u32 dev_num) argument 1525 ddr3_tip_dynamic_read_leveling_seq(u32 dev_num) argument 1563 ddr3_tip_dynamic_per_bit_read_leveling_seq(u32 dev_num) argument 1602 ddr3_tip_print_wl_supp_result(u32 dev_num) argument 1724 mv_ddr_rl_dqs_burst(u32 dev_num, u32 if_id, u32 freq) argument [all...] |
H A D | mv_ddr4_mpr_pda_if.c | 37 int mv_ddr4_mode_regs_init(u8 dev_num) argument 88 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR0_REG, 103 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR1_REG, 114 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR2_REG, 126 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR3_REG, 143 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR4_REG, 159 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR5_REG, 173 status = ddr3_tip_if_write(dev_num, access_type, if_id, DDR4_MR6_REG, 183 static int mv_ddr4_mpr_read_mode_enable(u8 dev_num, u32 mpr_num, u32 page_num, argument 203 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAS 222 mv_ddr4_mpr_mode_disable(u8 dev_num) argument 251 mv_ddr4_dq_decode(u8 dev_num, u32 *data) argument 286 mv_ddr4_mpr_read(u8 dev_num, u32 mpr_num, u32 page_num, enum mv_ddr4_mpr_read_format read_format, enum mv_ddr4_mpr_read_type read_type, u32 *data) argument 326 mv_ddr4_mpr_write_mode_enable(u8 dev_num, u32 mpr_location, u32 page_num, u32 data) argument 363 mv_ddr4_mpr_write(u8 dev_num, u32 mpr_location, u32 mpr_num, u32 page_num, u32 data) argument 380 mv_ddr4_dq_pins_mapping(u8 dev_num) argument 434 mv_ddr4_vref_training_mode_ctrl(u8 dev_num, u8 if_id, enum hws_access_type access_type, int enable) argument 475 mv_ddr4_vref_tap_set(u8 dev_num, u8 if_id, enum hws_access_type access_type, u32 taps_num, enum mv_ddr4_vref_tap_state state) argument 523 mv_ddr4_vref_set(u8 dev_num, u8 if_id, enum hws_access_type access_type, u32 range, u32 vdq_tv, u8 vdq_training_ena) argument 572 mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 subphy_mask, u32 cs_num) argument 629 mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable) argument [all...] |
H A D | mv_ddr4_training_leveling.c | 11 static int mv_ddr4_dynamic_pb_wl_supp(u32 dev_num, enum mv_wl_supp_mode ecc_mode); 18 static u8 mv_ddr4_xsb_comp_test(u32 dev_num, u32 subphy_num, u32 if_id, argument 84 ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST); 102 ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST); 113 ddr3_tip_load_pattern_to_mem(dev_num, PATTERN_TEST); 120 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE, 126 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE, 132 status = ddr3_tip_if_write(dev_num, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE, 169 status = ddr3_tip_ext_read(dev_num, if_id, pattern_table[PATTERN_TEST].start_addr << 3, 179 status = ddr3_tip_ext_read(dev_num, if_i 247 mv_ddr4_dynamic_wl_supp(u32 dev_num) argument 272 mv_ddr4_dynamic_pb_wl_supp(u32 dev_num, enum mv_wl_supp_mode ecc_mode) argument [all...] |
H A D | ddr3_debug.c | 133 int ddr3_tip_reg_dump(u32 dev_num) argument 137 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); 146 (dev_num, ACCESS_TYPE_UNICAST, 164 (dev_num, if_id, 175 (dev_num, if_id, 191 int ddr3_tip_init_config_func(u32 dev_num, argument 197 memcpy(&config_func_info[dev_num], config_func, 214 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr) argument 216 if (config_func_info[dev_num].tip_get_device_info_func != NULL) { 217 return config_func_info[dev_num] 324 print_device_info(u8 dev_num) argument 369 ddr3_tip_print_log(u32 dev_num, u32 mem_addr) argument 576 ddr3_tip_print_stability_log(u32 dev_num) argument 783 ddr3_tip_register_xsb_info(u32 dev_num, struct hws_xsb_info *xsb_info_table) argument 792 ddr3_tip_read_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], u32 reg_addr, u32 mask) argument 826 ddr3_tip_write_adll_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], u32 reg_addr) argument 861 read_phase_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr, u32 mask) argument 889 write_leveling_value(u32 dev_num, u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], u32 pup_ph_values[MAX_INTERFACE_NUM * MAX_BUS_NUM], int reg_addr) argument 954 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0; local 989 print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]) argument 1005 print_ph(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]) argument 1063 ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction, u32 mode) argument 1209 ddr3_tip_run_leveling_sweep_test(int dev_num, u32 repeat_num, u32 direction, u32 mode) argument 1407 u32 dev_num = 0; local 1459 run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type, u32 burst_length) argument 1500 run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type, u32 burst_length) argument [all...] |
H A D | ddr3_init.h | 146 int ddr3_tip_enable_init_sequence(u32 dev_num); 155 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data); 156 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask); 159 int mv_ddr4_mode_regs_init(u8 dev_num); 160 int mv_ddr4_sdram_config(u32 dev_num); 161 int mv_ddr4_phy_config(u32 dev_num); 162 int mv_ddr4_calibration_adjust(u32 dev_num, u8 vref_en, u8 pod_only); 163 int mv_ddr4_training_main_flow(u32 dev_num); 166 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]); 167 int print_ph(u32 dev_num, u3 [all...] |
H A D | ddr3_training_hw_algo.c | 43 int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) argument 52 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); 55 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 58 CHECK_STATUS(ddr3_tip_if_read(dev_num, access_type, if_id, 77 (dev_num, if_id, 101 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 105 CHECK_STATUS(ddr3_tip_if_write(dev_num, access_type, if_id, 113 int get_valid_win_rx(u32 dev_num, u32 if_id, u8 res[4]) argument 126 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id, 147 int ddr3_tip_vref(u32 dev_num) argument 629 ddr3_tip_cmd_addr_init_delay(u32 dev_num, u32 adll_tap) argument [all...] |
H A D | ddr3_training_ip_engine.h | 33 int ddr3_tip_training_ip_test(u32 dev_num, enum hws_training_result result_type, 40 int ddr3_tip_load_pattern_to_mem(u32 dev_num, enum hws_pattern pattern); 41 int ddr3_tip_load_all_pattern_to_mem(u32 dev_num); 42 int ddr3_tip_read_training_result(u32 dev_num, u32 if_id, 52 int ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, 63 int ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type,
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H A D | ddr3_training_centralization.c | 31 static int ddr3_tip_centralization(u32 dev_num, u32 mode); 36 int ddr3_tip_centralization_rx(u32 dev_num) argument 38 CHECK_STATUS(ddr3_tip_special_rx(dev_num)); 39 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_RX)); 47 int ddr3_tip_centralization_tx(u32 dev_num) argument 49 CHECK_STATUS(ddr3_tip_centralization(dev_num, CENTRAL_TX)); 57 static int ddr3_tip_centralization(u32 dev_num, u32 mode) argument 69 u32 octets_per_if_num = ddr3_tip_dev_attr_get(dev_num, MV_ATTR_OCTET_PER_INTERFACE); 89 (dev_num, ACCESS_TYPE_UNICAST, if_id, 93 (dev_num, ACCESS_TYPE_UNICAS 526 ddr3_tip_special_rx(u32 dev_num) argument 728 ddr3_tip_print_centralization_result(u32 dev_num) argument [all...] |
/u-boot/test/py/tests/ |
H A D | test_scsi.py | 16 'dev_num': 0, 27 dev_num = f.get('dev_num', None) 28 if not isinstance(dev_num, int): 39 return dev_num, dev_type, dev_size 43 dev_num, dev_type, dev_size = scsi_setup(u_boot_console) 45 assert f'Device {dev_num}:' in output 53 dev_num, dev_type, dev_size = scsi_setup(u_boot_console) 55 assert f'Device {dev_num}:' in output 63 dev_num, dev_typ [all...] |
/u-boot/lib/fwu_updates/ |
H A D | fwu_gpt.c | 36 static int fwu_alt_num_for_dfu_dev(struct dfu_entity *dfu, int dev_num, argument 45 dfu->data.mmc.dev_num == dev_num && 64 int i, part, dev_num; local 67 dev_num = desc->devnum; 87 ret = fwu_alt_num_for_dfu_dev(dfu, dev_num, part, dfu_dev,
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/u-boot/include/ |
H A D | netdev.h | 33 int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num); 35 int cs8900_initialize(u8 dev_num, int base_addr); 42 int ep93xx_eth_initialize(u8 dev_num, int base_addr); 44 int ethoc_initialize(u8 dev_num, int base_addr); 51 int ks8851_mll_initialize(u8 dev_num, int base_addr); 52 int lan91c96_initialize(u8 dev_num, int base_addr); 71 int smc91111_initialize(u8 dev_num, phys_addr_t base_addr); 72 int smc911x_initialize(u8 dev_num, phys_addr_t base_addr);
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