Searched refs:ddrc (Results 1 - 12 of 12) sorted by relevance
| /u-boot/board/atmel/sama5d27_wlsom1_ek/ |
| H A D | sama5d27_wlsom1_ek.c | 146 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) argument
148 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_LPDDR2_SDRAM);
150 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_9 |
158 ddrc->lpddr23_lpr = ATMEL_MPDDRC_LPDDR23_LPR_DS(0x3);
164 ddrc->rtr = 0x27f;
166 ddrc->rtr |= ATMEL_MPDDRC_RTR_ADJ_REF;
168 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
177 ddrc->tpr1 = ((21 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
182 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
188 ddrc
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| /u-boot/arch/arm/mach-zynq/ |
| H A D | Makefile | 10 obj-y += ddrc.o
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| /u-boot/board/atmel/sama5d2_xplained/ |
| H A D | sama5d2_xplained.c | 114 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) argument
116 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
118 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
127 ddrc->rtr = 0x511;
129 ddrc->tpr0 = (6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
138 ddrc->tpr1 = (27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET |
143 ddrc->tpr2 = (0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET |
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| /u-boot/board/atmel/sama5d27_som1_ek/ |
| H A D | sama5d27_som1_ek.c | 114 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) argument
116 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
118 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
127 ddrc->rtr = 0x511;
129 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
138 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
143 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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| /u-boot/board/atmel/sama5d2_icp/ |
| H A D | sama5d2_icp.c | 148 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) argument
150 ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
152 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
160 ddrc->rtr = 0x298;
162 ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
171 ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
176 ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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| /u-boot/board/conclusive/kstr-sama5d27/ |
| H A D | kstr-sama5d27.c | 149 static void ddrc_conf(struct atmel_mpddrc_config *ddrc) argument
151 ddrc->md = (ATMEL_MPDDRC_MD_DBW_16_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
153 ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
162 ddrc->rtr = 0x511;
164 ddrc->tpr0 = ((7 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
173 ddrc->tpr1 = ((22 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
178 ddrc->tpr2 = ((2 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
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| /u-boot/drivers/ram/renesas/rzn1/ |
| H A D | ddr_async.c | 28 void __iomem *ddrc; member in struct:cadence_ddr_info
54 #define ddrc_readl(off) cadence_readl(priv->ddrc, off)
55 #define ddrc_writel(val, off) cadence_writel(priv->ddrc, off, val)
220 cdns_ddr_ctrl_init(priv->ddrc, 1,
225 rzn1_ddr3_single_bank(priv->ddrc);
226 cdns_ddr_set_diff_cs_delays(priv->ddrc, 2, 7, 2, 2);
227 cdns_ddr_set_same_cs_delays(priv->ddrc, 0, 7, 0, 0);
228 cdns_ddr_set_odt_times(priv->ddrc, 5, 6, 6, 0, 4);
229 cdns_ddr_ctrl_start(priv->ddrc);
286 priv->ddrc
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| /u-boot/arch/arm/mach-imx/mx7/ |
| H A D | ddr.c | 28 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
33 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
139 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
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| /u-boot/arch/arm/include/asm/arch-mx7/ |
| H A D | mx7-ddr.h | 18 struct ddrc { struct
166 void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
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| /u-boot/board/ronetix/imx7-cm/ |
| H A D | spl.c | 23 static struct ddrc ddrc_regs_val = {
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| /u-boot/board/compulab/cl-som-imx7/ |
| H A D | spl.c | 40 static struct ddrc cl_som_imx7_spl_ddrc_regs_val = {
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| /u-boot/board/technexion/pico-imx7d/ |
| H A D | spl.c | 37 static struct ddrc ddrc_regs_val = {
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