1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Microchip Technology, Inc.
4 *		      Eugen Hristev <eugen.hristev@microchip.com>
5 */
6
7#include <common.h>
8#include <debug_uart.h>
9#include <init.h>
10#include <asm/global_data.h>
11#include <asm/io.h>
12#include <asm/arch/at91_common.h>
13#include <asm/arch/atmel_pio4.h>
14#include <asm/arch/atmel_mpddrc.h>
15#include <asm/arch/atmel_sdhci.h>
16#include <asm/arch/clk.h>
17#include <asm/arch/gpio.h>
18#include <asm/arch/sama5d2.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21
22static void rgb_leds_init(void)
23{
24	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0);	/* LED RED */
25	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 0);	/* LED GREEN */
26	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 1);	/* LED BLUE */
27}
28
29int board_late_init(void)
30{
31	return 0;
32}
33
34#ifdef CONFIG_DEBUG_UART_BOARD_INIT
35static void board_uart0_hw_init(void)
36{
37	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 26, ATMEL_PIO_PUEN_MASK); /* URXD0 */
38	atmel_pio4_set_c_periph(AT91_PIO_PORTB, 27, 0);	/* UTXD0 */
39
40	at91_periph_clk_enable(ATMEL_ID_UART0);
41}
42
43void board_debug_uart_init(void)
44{
45	board_uart0_hw_init();
46}
47#endif
48
49int board_early_init_f(void)
50{
51	return 0;
52}
53
54int board_init(void)
55{
56	/* address of boot parameters */
57	gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100;
58
59	rgb_leds_init();
60
61	return 0;
62}
63
64int dram_init(void)
65{
66	gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE,
67				    CFG_SYS_SDRAM_SIZE);
68	return 0;
69}
70
71#define MAC24AA_MAC_OFFSET	0xfa
72
73int misc_init_r(void)
74{
75#ifdef CONFIG_I2C_EEPROM
76	at91_set_ethaddr(MAC24AA_MAC_OFFSET);
77#endif
78	return 0;
79}
80
81/* SPL */
82#ifdef CONFIG_SPL_BUILD
83
84/* must set PB25 low to enable the CAN transceivers */
85static void board_can_stdby_dis(void)
86{
87	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 25, 0);
88}
89
90static void board_leds_init(void)
91{
92	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 0, 0); /* RED */
93	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 1, 1); /* GREEN */
94	atmel_pio4_set_pio_output(AT91_PIO_PORTA, 31, 0); /* BLUE */
95}
96
97/* deassert reset lines for external periph in case of warm reboot */
98static void board_reset_additional_periph(void)
99{
100	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 0); /* LAN9252_RST */
101	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 0); /* HSIC_RST */
102	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 0); /* USB2534_RST */
103	atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 0); /* KSZ8563_RST */
104}
105
106static void board_start_additional_periph(void)
107{
108	atmel_pio4_set_pio_output(AT91_PIO_PORTB, 16, 1); /* LAN9252_RST */
109	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 2, 1); /* HSIC_RST */
110	atmel_pio4_set_pio_output(AT91_PIO_PORTC, 17, 1); /* USB2534_RST */
111	atmel_pio4_set_pio_output(AT91_PIO_PORTD, 4, 1); /* KSZ8563_RST */
112}
113
114#ifdef CONFIG_SD_BOOT
115void spl_mmc_init(void)
116{
117	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 1, 0);	/* CMD */
118	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 2, 0);	/* DAT0 */
119	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 3, 0);	/* DAT1 */
120	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 4, 0);	/* DAT2 */
121	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 5, 0);	/* DAT3 */
122	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 0, 0);	/* CK */
123	atmel_pio4_set_a_periph(AT91_PIO_PORTA, 13, 0);	/* CD */
124
125	at91_periph_clk_enable(ATMEL_ID_SDMMC0);
126}
127#endif
128
129void spl_board_init(void)
130{
131#ifdef CONFIG_SD_BOOT
132	spl_mmc_init();
133#endif
134	board_reset_additional_periph();
135	board_can_stdby_dis();
136	board_leds_init();
137}
138
139void spl_display_print(void)
140{
141}
142
143void spl_board_prepare_for_boot(void)
144{
145	board_start_additional_periph();
146}
147
148static void ddrc_conf(struct atmel_mpddrc_config *ddrc)
149{
150	ddrc->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR3_SDRAM);
151
152	ddrc->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
153		    ATMEL_MPDDRC_CR_NR_ROW_14 |
154		    ATMEL_MPDDRC_CR_CAS_DDR_CAS5 |
155		    ATMEL_MPDDRC_CR_DIC_DS |
156		    ATMEL_MPDDRC_CR_NB_8BANKS |
157		    ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
158		    ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
159
160	ddrc->rtr = 0x298;
161
162	ddrc->tpr0 = ((6 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET) |
163		      (3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET) |
164		      (3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET) |
165		      (9 << ATMEL_MPDDRC_TPR0_TRC_OFFSET) |
166		      (3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET) |
167		      (4 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET) |
168		      (4 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET) |
169		      (4 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET));
170
171	ddrc->tpr1 = ((27 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET) |
172		      (29 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET) |
173		      (0 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET) |
174		      (10 << ATMEL_MPDDRC_TPR1_TXP_OFFSET));
175
176	ddrc->tpr2 = ((0 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET) |
177		      (0 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET) |
178		      (0 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET) |
179		      (4 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET) |
180		      (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET));
181}
182
183void mem_init(void)
184{
185	struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
186	struct atmel_mpddr *mpddrc = (struct atmel_mpddr *)ATMEL_BASE_MPDDRC;
187	struct atmel_mpddrc_config ddrc_config;
188	u32 reg;
189
190	ddrc_conf(&ddrc_config);
191
192	at91_periph_clk_enable(ATMEL_ID_MPDDRC);
193	writel(AT91_PMC_DDR, &pmc->scer);
194
195	reg = readl(&mpddrc->io_calibr);
196	reg &= ~ATMEL_MPDDRC_IO_CALIBR_RDIV;
197	reg |= ATMEL_MPDDRC_IO_CALIBR_DDR3_RZQ_55;
198	reg &= ~ATMEL_MPDDRC_IO_CALIBR_TZQIO;
199	reg |= ATMEL_MPDDRC_IO_CALIBR_TZQIO_(100);
200	writel(reg, &mpddrc->io_calibr);
201
202	writel(ATMEL_MPDDRC_RD_DATA_PATH_SHIFT_ONE_CYCLE,
203	       &mpddrc->rd_data_path);
204
205	ddr3_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddrc_config);
206
207	writel(0x5355, &mpddrc->cal_mr4);
208	writel(64, &mpddrc->tim_cal);
209}
210
211void at91_pmc_init(void)
212{
213	u32 tmp;
214
215	/*
216	 * while coming from the ROM code, we run on PLLA @ 492 MHz / 164 MHz
217	 * so we need to slow down and configure MCKR accordingly.
218	 * This is why we have a special flavor of the switching function.
219	 */
220	tmp = AT91_PMC_MCKR_PLLADIV_2 |
221	      AT91_PMC_MCKR_MDIV_3 |
222	      AT91_PMC_MCKR_CSS_MAIN;
223	at91_mck_init_down(tmp);
224
225	tmp = AT91_PMC_PLLAR_29 |
226	      AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
227	      AT91_PMC_PLLXR_MUL(82) |
228	      AT91_PMC_PLLXR_DIV(1);
229	at91_plla_init(tmp);
230
231	tmp = AT91_PMC_MCKR_H32MXDIV |
232	      AT91_PMC_MCKR_PLLADIV_2 |
233	      AT91_PMC_MCKR_MDIV_3 |
234	      AT91_PMC_MCKR_CSS_PLLA;
235	at91_mck_init(tmp);
236}
237#endif
238