1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2021 Ronetix GmbH 4 * 5 * Author: Ilko Iliev <iliev@ronetix.at> 6 */ 7 8#include <common.h> 9#include <cpu_func.h> 10#include <init.h> 11#include <asm/arch/clock.h> 12#include <asm/arch/imx-regs.h> 13#include <asm/arch/crm_regs.h> 14#include <asm/arch/mx7-pins.h> 15#include <asm/arch/sys_proto.h> 16#include <asm/arch-mx7/mx7-ddr.h> 17#include <asm/mach-imx/iomux-v3.h> 18#include <asm/gpio.h> 19#include <asm/sections.h> 20#include <fsl_esdhc_imx.h> 21#include <spl.h> 22 23static struct ddrc ddrc_regs_val = { 24 .mstr = 0x01040001, 25 .rfshtmg = 0x00400046, 26 .init1 = 0x00690000, 27 .init0 = 0x00020083, 28 .init3 = 0x09300004, 29 .init4 = 0x04080000, 30 .init5 = 0x00100004, 31 .rankctl = 0x0000033F, 32 .dramtmg0 = 0x09081109, 33 .dramtmg1 = 0x0007020d, 34 .dramtmg2 = 0x03040407, 35 .dramtmg3 = 0x00002006, 36 .dramtmg4 = 0x04020205, 37 .dramtmg5 = 0x03030202, 38 .dramtmg8 = 0x00000803, 39 .zqctl0 = 0x00800020, 40 .dfitmg0 = 0x02098204, 41 .dfitmg1 = 0x00030303, 42 .dfiupd0 = 0x80400003, 43 .dfiupd1 = 0x00100020, 44 .dfiupd2 = 0x80100004, 45 .addrmap4 = 0x00000F0F, 46 .odtcfg = 0x06000604, 47 .odtmap = 0x00000001, 48 .rfshtmg = 0x00400046, 49 .dramtmg0 = 0x09081109, 50 .addrmap0 = 0x0000001f, 51 .addrmap1 = 0x00080808, 52 .addrmap4 = 0x00000f0f, 53 .addrmap5 = 0x07070707, 54 .addrmap6 = 0x0f0f0707, 55}; 56 57static struct ddrc_mp ddrc_mp_val = { 58 .pctrl_0 = 0x00000001, 59}; 60 61static struct ddr_phy ddr_phy_regs_val = { 62 .phy_con0 = 0x17420f40, 63 .phy_con1 = 0x10210100, 64 .phy_con4 = 0x00060807, 65 .mdll_con0 = 0x1010007e, 66 .drvds_con0 = 0x00000d6e, 67 .cmd_sdll_con0 = 0x00000010, 68 .offset_lp_con0 = 0x0000000f, 69 .offset_rd_con0 = 0x0a0a0a0a, 70 .offset_wr_con0 = 0x06060606, 71}; 72 73static struct mx7_calibration calib_param = { 74 .num_val = 5, 75 .values = { 76 0x0E407304, 77 0x0E447304, 78 0x0E447306, 79 0x0E447304, 80 0x0E447304, 81 }, 82}; 83 84static void ddr_init(void) 85{ 86 mx7_dram_cfg(&ddrc_regs_val, &ddrc_mp_val, &ddr_phy_regs_val, &calib_param); 87} 88 89#define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 90 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 91 92static iomux_v3_cfg_t const uart1_pads[] = { 93 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 94 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 95}; 96 97void uart1_pads_set(void) 98{ 99 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 100} 101 102void board_init_f(ulong dummy) 103{ 104 arch_cpu_init(); 105 106 uart1_pads_set(); 107 108 timer_init(); 109 110 preloader_console_init(); 111 112 ddr_init(); 113 114 memset(__bss_start, 0, __bss_end - __bss_start); 115 116 board_init_r(NULL, 0); 117} 118 119void reset_cpu(void) 120{ 121} 122 123#define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 124 PAD_CTL_HYS | PAD_CTL_PUE | \ 125 PAD_CTL_PUS_PU47KOHM) 126 127static iomux_v3_cfg_t const usdhc1_pads[] = { 128 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 129 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 130 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 131 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 132 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 133 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 134 135 MX7D_PAD_SD1_CD_B__GPIO5_IO0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 136}; 137 138void usdhc1_pads_set(void) 139{ 140 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 141} 142 143static struct fsl_esdhc_cfg usdhc_cfg = { 144 USDHC1_BASE_ADDR, 0, 4 145}; 146 147int board_mmc_init(struct bd_info *bis) 148{ 149 usdhc1_pads_set(); 150 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 151 return fsl_esdhc_initialize(bis, &usdhc_cfg); 152} 153 154int board_mmc_getcd(struct mmc *mmc) 155{ 156 return 1; 157} 158