Searched refs:ctrl (Results 1 - 25 of 274) sorted by relevance

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/u-boot/arch/arm/mach-kirkwood/
H A Dcache.c14 u32 ctrl; local
16 ctrl = readfr_extra_feature_reg();
17 ctrl &= ~FEROCEON_EXTRA_FEATURE_L2C_EN;
18 writefr_extra_feature_reg(ctrl);
/u-boot/arch/arm/mach-omap2/am33xx/
H A Dhw_data.c12 struct omap_sys_ctrl_regs const **ctrl = variable
17 *ctrl = &am33xx_ctrl;
/u-boot/arch/arm/mach-omap2/omap3/
H A Dhw_data.c12 struct omap_sys_ctrl_regs const **ctrl = variable
17 *ctrl = &omap3_ctrl;
/u-boot/arch/arm/mach-omap2/omap4/
H A Dhwinit.c54 writel(lpddr2io, (*ctrl)->control_lpddr2io1_0);
55 writel(lpddr2io, (*ctrl)->control_lpddr2io1_1);
58 (*ctrl)->control_lpddr2io1_2);
59 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io1_3);
62 writel(lpddr2io, (*ctrl)->control_lpddr2io2_0);
63 writel(lpddr2io, (*ctrl)->control_lpddr2io2_1);
66 (*ctrl)->control_lpddr2io2_2);
67 writel(CONTROL_LPDDR2IO_3_VAL, (*ctrl)->control_lpddr2io2_3);
75 if (!(readl((*ctrl)->control_std_fuse_opp_bgap) & 0xFFFF)) {
78 (*ctrl)
[all...]
/u-boot/drivers/usb/host/
H A Dxhci-mem.c67 static void xhci_segment_free(struct xhci_ctrl *ctrl, struct xhci_segment *seg) argument
69 xhci_dma_unmap(ctrl, seg->dma, SEGMENT_SIZE);
82 static void xhci_ring_free(struct xhci_ctrl *ctrl, struct xhci_ring *ring) argument
93 xhci_segment_free(ctrl, seg);
96 xhci_segment_free(ctrl, first_seg);
104 * @ctrl host controller data structure
107 static void xhci_scratchpad_free(struct xhci_ctrl *ctrl) argument
109 struct xhci_hccr *hccr = ctrl->hccr;
112 if (!ctrl->scratchpad)
116 xhci_dma_unmap(ctrl, ctr
134 xhci_free_container_ctx(struct xhci_ctrl *ctrl, struct xhci_container_ctx *ctx) argument
148 xhci_free_virt_devices(struct xhci_ctrl *ctrl) argument
186 xhci_cleanup(struct xhci_ctrl *ctrl) argument
232 xhci_link_segments(struct xhci_ctrl *ctrl, struct xhci_segment *prev, struct xhci_segment *next, bool link_trbs) argument
289 xhci_segment_alloc(struct xhci_ctrl *ctrl) argument
319 xhci_ring_alloc(struct xhci_ctrl *ctrl, unsigned int num_segs, bool link_trbs) argument
365 xhci_scratchpad_alloc(struct xhci_ctrl *ctrl) argument
442 xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type) argument
468 xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id) argument
527 xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr, struct xhci_hcor *hcor) argument
652 xhci_get_slot_ctx(struct xhci_ctrl *ctrl, struct xhci_container_ctx *ctx) argument
670 xhci_get_ep_ctx(struct xhci_ctrl *ctrl, struct xhci_container_ctx *ctx, unsigned int ep_index) argument
695 xhci_endpoint_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx, struct xhci_container_ctx *out_ctx, unsigned int ep_index) argument
724 xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx, struct xhci_container_ctx *out_ctx) argument
745 xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl, struct usb_device *udev, int hop_portnr) argument
[all...]
H A Dehci-hcd.c122 static int ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg) argument
127 static void ehci_set_usbmode(struct ehci_ctrl *ctrl) argument
132 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd + USBMODE);
143 static void ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg, argument
149 static uint32_t *ehci_get_portsc_register(struct ehci_ctrl *ctrl, int port) argument
151 int max_ports = HCS_N_PORTS(ehci_readl(&ctrl->hccr->cr_hcsparams));
160 return (uint32_t *)&ctrl->hcor->or_portsc[port];
179 static int ehci_reset(struct ehci_ctrl *ctrl) argument
184 cmd = ehci_readl(&ctrl->hcor->or_usbcmd);
186 ehci_writel(&ctrl
207 ehci_shutdown(struct ehci_ctrl *ctrl) argument
300 ehci_enable_async(struct ehci_ctrl *ctrl) argument
321 ehci_disable_async(struct ehci_ctrl *ctrl) argument
345 ehci_iaa_cycle(struct ehci_ctrl *ctrl) argument
382 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); local
732 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); local
1013 ehci_setup_ops(struct ehci_ctrl *ctrl, const struct ehci_ops *ops) argument
1034 struct ehci_ctrl *ctrl = &ehcic[index]; local
1046 ehci_common_init(struct ehci_ctrl *ctrl, uint tweaks) argument
1164 struct ehci_ctrl *ctrl = &ehcic[index]; local
1217 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); local
1244 enable_periodic(struct ehci_ctrl *ctrl) argument
1265 disable_periodic(struct ehci_ctrl *ctrl) argument
1288 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); local
1489 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); local
1571 _ehci_lock_async(struct ehci_ctrl *ctrl, int lock) argument
1621 struct ehci_ctrl *ctrl = ehci_get_ctrl(dev); local
1690 struct ehci_ctrl *ctrl = dev_get_priv(dev); local
1700 struct ehci_ctrl *ctrl = dev_get_priv(dev); local
1743 struct ehci_ctrl *ctrl = dev_get_priv(dev); local
[all...]
H A Dxhci-ring.c50 * @param ctrl Host controller data structure
56 static int last_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, argument
59 if (ring == ctrl->event_ring)
69 * @param ctrl Host controller data structure
75 static bool last_trb_on_last_seg(struct xhci_ctrl *ctrl, argument
80 if (ring == ctrl->event_ring)
101 * @param ctrl Host controller data structure
109 static void inc_enq(struct xhci_ctrl *ctrl, struct xhci_ring *ring, argument
122 while (last_trb(ctrl, ring, ring->enq_seg, next)) {
123 if (ring != ctrl
167 inc_deq(struct xhci_ctrl *ctrl, struct xhci_ring *ring) argument
201 queue_trb(struct xhci_ctrl *ctrl, struct xhci_ring *ring, bool more_trbs_coming, unsigned int *trb_fields) argument
231 prepare_ring(struct xhci_ctrl *ctrl, struct xhci_ring *ep_ring, u32 ep_state) argument
294 xhci_queue_command(struct xhci_ctrl *ctrl, dma_addr_t addr, u32 slot_id, u32 ep_index, trb_type cmd) argument
348 xhci_td_remainder(struct xhci_ctrl *ctrl, int transferred, int trb_buff_len, unsigned int td_total_len, int maxp, bool more_trbs_coming) argument
386 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); local
416 xhci_acknowledge_event(struct xhci_ctrl *ctrl) argument
435 event_ready(struct xhci_ctrl *ctrl) argument
461 xhci_wait_for_event(struct xhci_ctrl *ctrl, trb_type expected) argument
511 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); local
550 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); local
649 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); local
859 struct xhci_ctrl *ctrl = xhci_get_ctrl(udev); local
[all...]
/u-boot/drivers/mtd/nand/raw/brcmnand/
H A Dbrcmnand.c265 struct brcmnand_controller *ctrl; member in struct:brcmnand_host
548 static inline u32 nand_readreg(struct brcmnand_controller *ctrl, u32 offs) argument
550 return brcmnand_readl(ctrl->nand_base + offs);
553 static inline void nand_writereg(struct brcmnand_controller *ctrl, u32 offs, argument
556 brcmnand_writel(val, ctrl->nand_base + offs);
559 static int brcmnand_revision_init(struct brcmnand_controller *ctrl) argument
569 ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
572 if (ctrl->nand_version < 0x0201) {
573 dev_err(ctrl
683 brcmnand_flash_dma_revision_init(struct brcmnand_controller *ctrl) argument
695 brcmnand_read_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg) argument
706 brcmnand_write_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg, u32 val) argument
715 brcmnand_rmw_reg(struct brcmnand_controller *ctrl, enum brcmnand_reg reg, u32 mask, unsigned int shift, u32 val) argument
726 brcmnand_read_fc(struct brcmnand_controller *ctrl, int word) argument
731 brcmnand_write_fc(struct brcmnand_controller *ctrl, int word, u32 val) argument
737 brcmnand_clear_ecc_addr(struct brcmnand_controller *ctrl) argument
747 brcmnand_get_uncorrecc_addr(struct brcmnand_controller *ctrl) argument
759 brcmnand_get_correcc_addr(struct brcmnand_controller *ctrl) argument
775 struct brcmnand_controller *ctrl = host->ctrl; local
785 brcmnand_cs_offset(struct brcmnand_controller *ctrl, int cs, enum brcmnand_cs_reg reg) argument
803 brcmnand_count_corrected(struct brcmnand_controller *ctrl) argument
812 struct brcmnand_controller *ctrl = host->ctrl; local
841 brcmnand_cmd_shift(struct brcmnand_controller *ctrl) argument
872 brcmnand_spare_area_mask(struct brcmnand_controller *ctrl) argument
887 brcmnand_ecc_level_mask(struct brcmnand_controller *ctrl) argument
902 struct brcmnand_controller *ctrl = host->ctrl; local
919 brcmnand_sector_1k_shift(struct brcmnand_controller *ctrl) argument
933 struct brcmnand_controller *ctrl = host->ctrl; local
946 struct brcmnand_controller *ctrl = host->ctrl; local
970 bcmnand_ctrl_poll_status(struct brcmnand_controller *ctrl, u32 mask, u32 expected_val, unsigned long timeout_ms) argument
1013 brcmnand_set_wp(struct brcmnand_controller *ctrl, bool en) argument
1024 has_flash_dma(struct brcmnand_controller *ctrl) argument
1039 flash_dma_writel(struct brcmnand_controller *ctrl, enum flash_dma_reg dma_reg, u32 val) argument
1047 flash_dma_readl(struct brcmnand_controller *ctrl, enum flash_dma_reg dma_reg) argument
1067 is_hamming_ecc(struct brcmnand_controller *ctrl, struct brcmnand_cfg *cfg) argument
1211 struct brcmnand_controller *ctrl = host->ctrl; local
1250 oob_reg_read(struct brcmnand_controller *ctrl, u32 offs) argument
1268 oob_reg_write(struct brcmnand_controller *ctrl, u32 offs, u32 data) argument
1295 read_oob_from_regs(struct brcmnand_controller *ctrl, int i, u8 *oob, int sas, int sector_1k) argument
1318 write_oob_to_regs(struct brcmnand_controller *ctrl, int i, const u8 *oob, int sas, int sector_1k) argument
1341 struct brcmnand_controller *ctrl = data; local
1354 struct brcmnand_controller *ctrl = data; local
1364 struct brcmnand_controller *ctrl = data; local
1374 struct brcmnand_controller *ctrl = host->ctrl; local
1397 brcmnand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) argument
1407 struct brcmnand_controller *ctrl = host->ctrl; local
1454 struct brcmnand_controller *ctrl = host->ctrl; local
1493 struct brcmnand_controller *ctrl = host->ctrl; local
1602 struct brcmnand_controller *ctrl = host->ctrl; local
1721 struct brcmnand_controller *ctrl = host->ctrl; local
1750 struct brcmnand_controller *ctrl = host->ctrl; local
1784 struct brcmnand_controller *ctrl = host->ctrl; local
1890 struct brcmnand_controller *ctrl = host->ctrl; local
2027 struct brcmnand_controller *ctrl = host->ctrl; local
2145 struct brcmnand_controller *ctrl = host->ctrl; local
2278 struct brcmnand_controller *ctrl = host->ctrl; local
2406 struct brcmnand_controller *ctrl = host->ctrl; local
2531 struct brcmnand_controller *ctrl = host->ctrl; local
2561 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); local
2580 struct brcmnand_controller *ctrl = dev_get_drvdata(dev); local
2650 struct brcmnand_controller *ctrl; local
2914 struct brcmnand_controller *ctrl = dev_get_drvdata(&pdev->dev); local
[all...]
/u-boot/drivers/ddr/microchip/
H A Dddr2.c66 static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, argument
73 writel(i * MIN_LIM_WIDTH, &ctrl->tsel);
74 writel(param->min_limit, &ctrl->minlim);
77 writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel);
78 writel(param->req_period, &ctrl->reqprd);
81 writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel);
82 writel(param->min_cmd_acpt, &ctrl->mincmd);
100 static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, argument
106 writel(hostcmd1, &ctrl->cmd10[cmd_idx]);
107 writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl
116 struct ddr2_ctrl_regs *ctrl; local
[all...]
/u-boot/board/cssi/cmpc885/
H A Dnand.c19 static u32 nand_mask(unsigned int ctrl) argument
21 return ((ctrl & NAND_CLE) ? BIT_CLE : 0) |
22 ((ctrl & NAND_ALE) ? BIT_ALE : 0) |
23 (!(ctrl & NAND_NCE) ? BIT_NCE : 0);
26 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) argument
31 if (ctrl & NAND_CTRL_CHANGE)
33 BIT_CLE | BIT_ALE | BIT_NCE, nand_mask(ctrl));
/u-boot/arch/arm/mach-omap2/omap5/
H A Dhwinit.c61 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_0);
62 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch1_1);
63 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_0);
64 writel(ioregs->ctrl_ddrch, (*ctrl)->control_ddrch2_1);
65 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_0);
66 writel(ioregs->ctrl_lpddr2ch, (*ctrl)->control_lpddr2ch1_1);
67 writel(ioregs->ctrl_ddrio_0, (*ctrl)->control_ddrio_0);
68 writel(ioregs->ctrl_ddrio_1, (*ctrl)->control_ddrio_1);
69 writel(ioregs->ctrl_ddrio_2, (*ctrl)->control_ddrio_2);
79 writel(ioregs->ctrl_ddr3ch, (*ctrl)
[all...]
/u-boot/board/cssi/cmpcpro/
H A Dnand.c17 static u32 nand_mask(unsigned int ctrl) argument
19 return ((ctrl & NAND_CLE) ? BIT_CLE : 0) |
20 ((ctrl & NAND_ALE) ? BIT_ALE : 0);
23 static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl) argument
28 if (ctrl & NAND_CTRL_CHANGE)
30 BIT_CLE | BIT_ALE, nand_mask(ctrl));
/u-boot/arch/arm/mach-socfpga/include/mach/
H A Dtimer.h12 u32 ctrl; member in struct:socfpga_timer
/u-boot/arch/arm/mach-socfpga/
H A Dtimer.c22 writel(readl(&timer_base->ctrl) | 0x3, &timer_base->ctrl);
/u-boot/drivers/video/nexell/
H A Ds5pxx18_dp.c50 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl)
68 if (NULL == sync || NULL == ctrl) {
74 out_format = ctrl->out_format;
75 delay_mask = ctrl->delay_mask;
77 invert_field = ctrl->invert_field;
78 swap_rb = ctrl->swap_RB;
79 yc_order = ctrl->yc_order;
80 vck_select = ctrl->vck_select;
81 vclk_invert = ctrl->clk_inv_lv0 | ctrl
49 dp_control_setup(int module, struct dp_sync_info *sync, struct dp_ctrl_info *ctrl) argument
[all...]
/u-boot/drivers/i2c/
H A Di2c-microchip.c106 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); local
108 ctrl &= ~CTRL_SI;
109 writel(ctrl, bus->base + MPFS_I2C_CTRL);
114 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); local
116 ctrl &= ~CTRL_ENS1;
117 writel(ctrl, bus->base + MPFS_I2C_CTRL);
122 u8 ctrl = readl(bus->base + MPFS_I2C_CTRL); local
124 ctrl |= CTRL_ENS1;
125 writel(ctrl, bus->base + MPFS_I2C_CTRL);
136 u8 ctrl local
171 u8 clkval, ctrl; local
216 u8 ctrl; local
244 u8 ctrl; local
341 u8 ctrl; local
374 u8 ctrl; local
421 u8 ctrl, reg = 0; local
[all...]
/u-boot/arch/arm/mach-lpc32xx/
H A Ddevices.c16 static struct uart_ctrl_regs *ctrl = (struct uart_ctrl_regs *)UART_CTRL_BASE; variable in typeref:struct:uart_ctrl_regs
25 clrbits_le32(&ctrl->loop, UART_LOOPBACK(uart_id));
34 clrsetbits_le32(&ctrl->clkmode,
96 clrbits_le32(&ctrl->ctrl, UART_CTRL_UART5_USB_MODE);
102 uint32_t ctrl = readl(&clk->i2cclk_ctrl); local
104 ctrl |= CLK_I2C1_ENABLE;
106 ctrl |= CLK_I2C2_ENABLE;
107 writel(ctrl, &clk->i2cclk_ctrl);
/u-boot/drivers/sound/
H A Dtegra_i2s.c30 clrsetbits_le32(&regs->ctrl, I2S_CTRL_XFER_EN_TX,
38 u32 ctrl = readl(&regs->ctrl); local
41 ctrl &= ~(I2S_CTRL_FRAME_FORMAT_MASK | I2S_CTRL_LRCK_MASK);
42 ctrl |= I2S_CTRL_FRAME_FORMAT_LRCK;
43 ctrl |= I2S_CTRL_LRCK_L_LOW;
46 ctrl &= ~(I2S_CTRL_XFER_EN_TX | I2S_CTRL_XFER_EN_RX);
49 ctrl |= I2S_CTRL_MASTER_ENABLE;
52 ctrl &= ~I2S_CTRL_BIT_SIZE_MASK;
53 ctrl |
[all...]
/u-boot/arch/arm/mach-omap2/
H A Dsysinfo-common.c26 return (readl((*ctrl)->control_status) & DEVICE_TYPE_MASK) >>
/u-boot/drivers/mtd/nand/raw/
H A Dkirkwood_nand.c20 u32 ctrl; /* 0x10470 */ member in struct:kwnandf_registers
34 unsigned int ctrl)
42 if (ctrl & NAND_CLE)
44 else if (ctrl & NAND_ALE)
72 data = readl(&nf_reg->ctrl);
74 writel(data, &nf_reg->ctrl);
33 kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) argument
H A Dfsl_ifc_nand.c32 struct fsl_ifc_ctrl *ctrl; member in struct:fsl_ifc_mtd
223 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
224 struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
227 ctrl->page = page_addr;
235 ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
236 ctrl->index = column;
240 ctrl->index += mtd->writesize;
244 static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl, argument
257 struct fsl_ifc_ctrl *ctrl local
332 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
370 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
576 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
604 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
628 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
652 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
674 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
741 struct fsl_ifc_ctrl *ctrl = priv->ctrl; local
[all...]
H A Dfsl_elbc_nand.c54 struct fsl_elbc_ctrl *ctrl; member in struct:fsl_elbc_mtd
164 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
165 fsl_lbc_t *lbc = ctrl->regs;
168 ctrl->page = page_addr;
184 ctrl->addr = priv->vbase + buf_num * 1024;
185 ctrl->index = column;
189 ctrl->index += priv->page_size ? 2048 : 512;
191 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), "
193 buf_num, ctrl
204 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
255 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
289 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
507 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
544 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
561 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
583 struct fsl_elbc_ctrl *ctrl = priv->ctrl; local
[all...]
/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c25 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
27 if (bank >= ctrl->nr_banks) {
28 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks);
45 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
49 for (i = 0; i < ctrl->niomux_recalced; i++) {
50 data = &ctrl->iomux_recalced[i];
56 if (i >= ctrl->niomux_recalced)
69 struct rockchip_pin_ctrl *ctrl local
156 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
200 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
283 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
329 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
344 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
426 struct rockchip_pin_ctrl *ctrl = priv->ctrl; local
506 struct rockchip_pin_ctrl *ctrl = local
615 struct rockchip_pin_ctrl *ctrl; local
[all...]
/u-boot/drivers/fpga/
H A Dsocfpga_gen5.c22 clrsetbits_le32(&fpgamgr_regs->ctrl,
42 setbits_le32(&fpgamgr_regs->ctrl,
57 clrbits_le32(&fpgamgr_regs->ctrl,
73 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
76 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
79 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
94 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
112 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
146 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
194 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MAS
[all...]
/u-boot/drivers/pwm/
H A Drk_pwm.c63 u32 ctrl; local
67 ctrl = readl(priv->base + regs->ctrl);
73 ctrl |= PWM_LOCK;
74 writel(ctrl, priv->base + regs->ctrl);
86 ctrl &= ~(PWM_DUTY_MASK | PWM_INACTIVE_MASK);
87 ctrl |= priv->conf_polarity;
96 ctrl &= ~PWM_LOCK;
97 writel(ctrl, pri
108 u32 ctrl; local
[all...]

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