1// SPDX-License-Identifier: GPL-2.0+ 2/* Freescale Enhanced Local Bus Controller FCM NAND driver 3 * 4 * Copyright (c) 2006-2008 Freescale Semiconductor 5 * 6 * Authors: Nick Spence <nick.spence@freescale.com>, 7 * Scott Wood <scottwood@freescale.com> 8 */ 9 10#include <common.h> 11#include <command.h> 12#include <malloc.h> 13#include <nand.h> 14#include <dm/devres.h> 15 16#include <linux/mtd/mtd.h> 17#include <linux/mtd/rawnand.h> 18#include <linux/mtd/nand_ecc.h> 19 20#include <asm/io.h> 21#include <linux/errno.h> 22 23#ifdef CONFIG_NAND_FSL_ELBC_DT 24#include <dm/read.h> 25#endif 26 27#ifdef VERBOSE_DEBUG 28#define DEBUG_ELBC 29#define vdbg(format, arg...) printf("DEBUG: " format, ##arg) 30#else 31#define vdbg(format, arg...) do {} while (0) 32#endif 33 34/* Can't use plain old DEBUG because the linux mtd 35 * headers define it as a macro. 36 */ 37#ifdef DEBUG_ELBC 38#define dbg(format, arg...) printf("DEBUG: " format, ##arg) 39#else 40#define dbg(format, arg...) do {} while (0) 41#endif 42 43#define MAX_BANKS 8 44#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ 45 46#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) 47 48struct fsl_elbc_ctrl; 49 50/* mtd information per set */ 51 52struct fsl_elbc_mtd { 53 struct nand_chip chip; 54 struct fsl_elbc_ctrl *ctrl; 55 56 struct device *dev; 57 int bank; /* Chip select bank number */ 58 u8 __iomem *vbase; /* Chip select base virtual address */ 59 int page_size; /* NAND page size (0=512, 1=2048) */ 60 unsigned int fmr; /* FCM Flash Mode Register value */ 61}; 62 63/* overview of the fsl elbc controller */ 64 65struct fsl_elbc_ctrl { 66 struct nand_hw_control controller; 67 struct fsl_elbc_mtd *chips[MAX_BANKS]; 68 69 /* device info */ 70 fsl_lbc_t *regs; 71 u8 __iomem *addr; /* Address of assigned FCM buffer */ 72 unsigned int page; /* Last page written to / read from */ 73 unsigned int read_bytes; /* Number of bytes read during command */ 74 unsigned int column; /* Saved column from SEQIN */ 75 unsigned int index; /* Pointer to next byte to 'read' */ 76 unsigned int status; /* status read from LTESR after last op */ 77 unsigned int mdr; /* UPM/FCM Data Register value */ 78 unsigned int use_mdr; /* Non zero if the MDR is to be set */ 79 unsigned int oob; /* Non zero if operating on OOB data */ 80}; 81 82/* These map to the positions used by the FCM hardware ECC generator */ 83 84/* Small Page FLASH with FMR[ECCM] = 0 */ 85static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { 86 .eccbytes = 3, 87 .eccpos = {6, 7, 8}, 88 .oobfree = { {0, 5}, {9, 7} }, 89}; 90 91/* Small Page FLASH with FMR[ECCM] = 1 */ 92static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { 93 .eccbytes = 3, 94 .eccpos = {8, 9, 10}, 95 .oobfree = { {0, 5}, {6, 2}, {11, 5} }, 96}; 97 98/* Large Page FLASH with FMR[ECCM] = 0 */ 99static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { 100 .eccbytes = 12, 101 .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, 102 .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, 103}; 104 105/* Large Page FLASH with FMR[ECCM] = 1 */ 106static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { 107 .eccbytes = 12, 108 .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, 109 .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, 110}; 111 112/* 113 * fsl_elbc_oob_lp_eccm* specify that LP NAND's OOB free area starts at offset 114 * 1, so we have to adjust bad block pattern. This pattern should be used for 115 * x8 chips only. So far hardware does not support x16 chips anyway. 116 */ 117static u8 scan_ff_pattern[] = { 0xff, }; 118 119static struct nand_bbt_descr largepage_memorybased = { 120 .options = 0, 121 .offs = 0, 122 .len = 1, 123 .pattern = scan_ff_pattern, 124}; 125 126/* 127 * ELBC may use HW ECC, so that OOB offsets, that NAND core uses for bbt, 128 * interfere with ECC positions, that's why we implement our own descriptors. 129 * OOB {11, 5}, works for both SP and LP chips, with ECCM = 1 and ECCM = 0. 130 */ 131static u8 bbt_pattern[] = {'B', 'b', 't', '0' }; 132static u8 mirror_pattern[] = {'1', 't', 'b', 'B' }; 133 134static struct nand_bbt_descr bbt_main_descr = { 135 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 136 NAND_BBT_2BIT | NAND_BBT_VERSION, 137 .offs = 11, 138 .len = 4, 139 .veroffs = 15, 140 .maxblocks = 4, 141 .pattern = bbt_pattern, 142}; 143 144static struct nand_bbt_descr bbt_mirror_descr = { 145 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE | 146 NAND_BBT_2BIT | NAND_BBT_VERSION, 147 .offs = 11, 148 .len = 4, 149 .veroffs = 15, 150 .maxblocks = 4, 151 .pattern = mirror_pattern, 152}; 153 154/*=================================*/ 155 156/* 157 * Set up the FCM hardware block and page address fields, and the fcm 158 * structure addr field to point to the correct FCM buffer in memory 159 */ 160static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) 161{ 162 struct nand_chip *chip = mtd_to_nand(mtd); 163 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 164 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 165 fsl_lbc_t *lbc = ctrl->regs; 166 int buf_num; 167 168 ctrl->page = page_addr; 169 170 if (priv->page_size) { 171 out_be32(&lbc->fbar, page_addr >> 6); 172 out_be32(&lbc->fpar, 173 ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | 174 (oob ? FPAR_LP_MS : 0) | column); 175 buf_num = (page_addr & 1) << 2; 176 } else { 177 out_be32(&lbc->fbar, page_addr >> 5); 178 out_be32(&lbc->fpar, 179 ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | 180 (oob ? FPAR_SP_MS : 0) | column); 181 buf_num = page_addr & 7; 182 } 183 184 ctrl->addr = priv->vbase + buf_num * 1024; 185 ctrl->index = column; 186 187 /* for OOB data point to the second half of the buffer */ 188 if (oob) 189 ctrl->index += priv->page_size ? 2048 : 512; 190 191 vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), " 192 "index %x, pes %d ps %d\n", 193 buf_num, ctrl->addr, priv->vbase, ctrl->index, 194 chip->phys_erase_shift, chip->page_shift); 195} 196 197/* 198 * execute FCM command and wait for it to complete 199 */ 200static int fsl_elbc_run_command(struct mtd_info *mtd) 201{ 202 struct nand_chip *chip = mtd_to_nand(mtd); 203 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 204 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 205 fsl_lbc_t *lbc = ctrl->regs; 206 u32 timeo = (CONFIG_SYS_HZ * 10) / 1000; 207 u32 time_start; 208 u32 ltesr; 209 210 /* Setup the FMR[OP] to execute without write protection */ 211 out_be32(&lbc->fmr, priv->fmr | 3); 212 if (ctrl->use_mdr) 213 out_be32(&lbc->mdr, ctrl->mdr); 214 215 vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", 216 in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); 217 vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x " 218 "fbcr=%08x bank=%d\n", 219 in_be32(&lbc->fbar), in_be32(&lbc->fpar), 220 in_be32(&lbc->fbcr), priv->bank); 221 222 /* execute special operation */ 223 out_be32(&lbc->lsor, priv->bank); 224 225 /* wait for FCM complete flag or timeout */ 226 time_start = get_timer(0); 227 228 ltesr = 0; 229 while (get_timer(time_start) < timeo) { 230 ltesr = in_be32(&lbc->ltesr); 231 if (ltesr & LTESR_CC) 232 break; 233 } 234 235 ctrl->status = ltesr & LTESR_NAND_MASK; 236 out_be32(&lbc->ltesr, ctrl->status); 237 out_be32(&lbc->lteatr, 0); 238 239 /* store mdr value in case it was needed */ 240 if (ctrl->use_mdr) 241 ctrl->mdr = in_be32(&lbc->mdr); 242 243 ctrl->use_mdr = 0; 244 245 vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", 246 ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); 247 248 /* returns 0 on success otherwise non-zero) */ 249 return ctrl->status == LTESR_CC ? 0 : -EIO; 250} 251 252static void fsl_elbc_do_read(struct nand_chip *chip, int oob) 253{ 254 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 255 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 256 fsl_lbc_t *lbc = ctrl->regs; 257 258 if (priv->page_size) { 259 out_be32(&lbc->fir, 260 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 261 (FIR_OP_CA << FIR_OP1_SHIFT) | 262 (FIR_OP_PA << FIR_OP2_SHIFT) | 263 (FIR_OP_CW1 << FIR_OP3_SHIFT) | 264 (FIR_OP_RBW << FIR_OP4_SHIFT)); 265 266 out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | 267 (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); 268 } else { 269 out_be32(&lbc->fir, 270 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 271 (FIR_OP_CA << FIR_OP1_SHIFT) | 272 (FIR_OP_PA << FIR_OP2_SHIFT) | 273 (FIR_OP_RBW << FIR_OP3_SHIFT)); 274 275 if (oob) 276 out_be32(&lbc->fcr, 277 NAND_CMD_READOOB << FCR_CMD0_SHIFT); 278 else 279 out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); 280 } 281} 282 283/* cmdfunc send commands to the FCM */ 284static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, 285 int column, int page_addr) 286{ 287 struct nand_chip *chip = mtd_to_nand(mtd); 288 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 289 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 290 fsl_lbc_t *lbc = ctrl->regs; 291 292 ctrl->use_mdr = 0; 293 294 /* clear the read buffer */ 295 ctrl->read_bytes = 0; 296 if (command != NAND_CMD_PAGEPROG) 297 ctrl->index = 0; 298 299 switch (command) { 300 /* READ0 and READ1 read the entire buffer to use hardware ECC. */ 301 case NAND_CMD_READ1: 302 column += 256; 303 304 /* fall-through */ 305 case NAND_CMD_READ0: 306 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" 307 " 0x%x, column: 0x%x.\n", page_addr, column); 308 309 out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ 310 set_addr(mtd, 0, page_addr, 0); 311 312 ctrl->read_bytes = mtd->writesize + mtd->oobsize; 313 ctrl->index += column; 314 315 fsl_elbc_do_read(chip, 0); 316 fsl_elbc_run_command(mtd); 317 return; 318 319 /* RNDOUT moves the pointer inside the page */ 320 case NAND_CMD_RNDOUT: 321 vdbg("fsl_elbc_cmdfunc: NAND_CMD_RNDOUT, column: 0x%x.\n", 322 column); 323 324 ctrl->index = column; 325 return; 326 327 /* READOOB reads only the OOB because no ECC is performed. */ 328 case NAND_CMD_READOOB: 329 vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" 330 " 0x%x, column: 0x%x.\n", page_addr, column); 331 332 out_be32(&lbc->fbcr, mtd->oobsize - column); 333 set_addr(mtd, column, page_addr, 1); 334 335 ctrl->read_bytes = mtd->writesize + mtd->oobsize; 336 337 fsl_elbc_do_read(chip, 1); 338 fsl_elbc_run_command(mtd); 339 340 return; 341 342 /* READID must read all 5 possible bytes while CEB is active */ 343 case NAND_CMD_READID: 344 case NAND_CMD_PARAM: 345 vdbg("fsl_elbc_cmdfunc: NAND_CMD 0x%x.\n", command); 346 347 out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | 348 (FIR_OP_UA << FIR_OP1_SHIFT) | 349 (FIR_OP_RBW << FIR_OP2_SHIFT)); 350 out_be32(&lbc->fcr, command << FCR_CMD0_SHIFT); 351 /* 352 * although currently it's 8 bytes for READID, we always read 353 * the maximum 256 bytes(for PARAM) 354 */ 355 out_be32(&lbc->fbcr, 256); 356 ctrl->read_bytes = 256; 357 ctrl->use_mdr = 1; 358 ctrl->mdr = column; 359 set_addr(mtd, 0, 0, 0); 360 fsl_elbc_run_command(mtd); 361 return; 362 363 /* ERASE1 stores the block and page address */ 364 case NAND_CMD_ERASE1: 365 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " 366 "page_addr: 0x%x.\n", page_addr); 367 set_addr(mtd, 0, page_addr, 0); 368 return; 369 370 /* ERASE2 uses the block and page address from ERASE1 */ 371 case NAND_CMD_ERASE2: 372 vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); 373 374 out_be32(&lbc->fir, 375 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 376 (FIR_OP_PA << FIR_OP1_SHIFT) | 377 (FIR_OP_CM1 << FIR_OP2_SHIFT)); 378 379 out_be32(&lbc->fcr, 380 (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | 381 (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); 382 383 out_be32(&lbc->fbcr, 0); 384 ctrl->read_bytes = 0; 385 386 fsl_elbc_run_command(mtd); 387 return; 388 389 /* SEQIN sets up the addr buffer and all registers except the length */ 390 case NAND_CMD_SEQIN: { 391 u32 fcr; 392 vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " 393 "page_addr: 0x%x, column: 0x%x.\n", 394 page_addr, column); 395 396 ctrl->column = column; 397 ctrl->oob = 0; 398 399 if (priv->page_size) { 400 fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | 401 (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); 402 403 out_be32(&lbc->fir, 404 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 405 (FIR_OP_CA << FIR_OP1_SHIFT) | 406 (FIR_OP_PA << FIR_OP2_SHIFT) | 407 (FIR_OP_WB << FIR_OP3_SHIFT) | 408 (FIR_OP_CW1 << FIR_OP4_SHIFT)); 409 } else { 410 fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) | 411 (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); 412 413 out_be32(&lbc->fir, 414 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 415 (FIR_OP_CM2 << FIR_OP1_SHIFT) | 416 (FIR_OP_CA << FIR_OP2_SHIFT) | 417 (FIR_OP_PA << FIR_OP3_SHIFT) | 418 (FIR_OP_WB << FIR_OP4_SHIFT) | 419 (FIR_OP_CW1 << FIR_OP5_SHIFT)); 420 421 if (column >= mtd->writesize) { 422 /* OOB area --> READOOB */ 423 column -= mtd->writesize; 424 fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; 425 ctrl->oob = 1; 426 } else if (column < 256) { 427 /* First 256 bytes --> READ0 */ 428 fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; 429 } else { 430 /* Second 256 bytes --> READ1 */ 431 fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; 432 } 433 } 434 435 out_be32(&lbc->fcr, fcr); 436 set_addr(mtd, column, page_addr, ctrl->oob); 437 return; 438 } 439 440 /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ 441 case NAND_CMD_PAGEPROG: { 442 vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " 443 "writing %d bytes.\n", ctrl->index); 444 445 /* if the write did not start at 0 or is not a full page 446 * then set the exact length, otherwise use a full page 447 * write so the HW generates the ECC. 448 */ 449 if (ctrl->oob || ctrl->column != 0 || 450 ctrl->index != mtd->writesize + mtd->oobsize) 451 out_be32(&lbc->fbcr, ctrl->index); 452 else 453 out_be32(&lbc->fbcr, 0); 454 455 fsl_elbc_run_command(mtd); 456 457 return; 458 } 459 460 /* CMD_STATUS must read the status byte while CEB is active */ 461 /* Note - it does not wait for the ready line */ 462 case NAND_CMD_STATUS: 463 out_be32(&lbc->fir, 464 (FIR_OP_CM0 << FIR_OP0_SHIFT) | 465 (FIR_OP_RBW << FIR_OP1_SHIFT)); 466 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); 467 out_be32(&lbc->fbcr, 1); 468 set_addr(mtd, 0, 0, 0); 469 ctrl->read_bytes = 1; 470 471 fsl_elbc_run_command(mtd); 472 473 /* The chip always seems to report that it is 474 * write-protected, even when it is not. 475 */ 476 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); 477 return; 478 479 /* RESET without waiting for the ready line */ 480 case NAND_CMD_RESET: 481 dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); 482 out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); 483 out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); 484 fsl_elbc_run_command(mtd); 485 return; 486 487 default: 488 printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", 489 command); 490 } 491} 492 493static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) 494{ 495 /* The hardware does not seem to support multiple 496 * chips per bank. 497 */ 498} 499 500/* 501 * Write buf to the FCM Controller Data Buffer 502 */ 503static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) 504{ 505 struct nand_chip *chip = mtd_to_nand(mtd); 506 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 507 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 508 unsigned int bufsize = mtd->writesize + mtd->oobsize; 509 510 if (len <= 0) { 511 printf("write_buf of %d bytes", len); 512 ctrl->status = 0; 513 return; 514 } 515 516 if ((unsigned int)len > bufsize - ctrl->index) { 517 printf("write_buf beyond end of buffer " 518 "(%d requested, %u available)\n", 519 len, bufsize - ctrl->index); 520 len = bufsize - ctrl->index; 521 } 522 523 memcpy_toio(&ctrl->addr[ctrl->index], buf, len); 524 /* 525 * This is workaround for the weird elbc hangs during nand write, 526 * Scott Wood says: "...perhaps difference in how long it takes a 527 * write to make it through the localbus compared to a write to IMMR 528 * is causing problems, and sync isn't helping for some reason." 529 * Reading back the last byte helps though. 530 */ 531 in_8(&ctrl->addr[ctrl->index] + len - 1); 532 533 ctrl->index += len; 534} 535 536/* 537 * read a byte from either the FCM hardware buffer if it has any data left 538 * otherwise issue a command to read a single byte. 539 */ 540static u8 fsl_elbc_read_byte(struct mtd_info *mtd) 541{ 542 struct nand_chip *chip = mtd_to_nand(mtd); 543 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 544 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 545 546 /* If there are still bytes in the FCM, then use the next byte. */ 547 if (ctrl->index < ctrl->read_bytes) 548 return in_8(&ctrl->addr[ctrl->index++]); 549 550 printf("read_byte beyond end of buffer\n"); 551 return ERR_BYTE; 552} 553 554/* 555 * Read from the FCM Controller Data Buffer 556 */ 557static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) 558{ 559 struct nand_chip *chip = mtd_to_nand(mtd); 560 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 561 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 562 int avail; 563 564 if (len < 0) 565 return; 566 567 avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); 568 memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); 569 ctrl->index += avail; 570 571 if (len > avail) 572 printf("read_buf beyond end of buffer " 573 "(%d requested, %d available)\n", 574 len, avail); 575} 576 577/* This function is called after Program and Erase Operations to 578 * check for success or failure. 579 */ 580static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) 581{ 582 struct fsl_elbc_mtd *priv = nand_get_controller_data(chip); 583 struct fsl_elbc_ctrl *ctrl = priv->ctrl; 584 fsl_lbc_t *lbc = ctrl->regs; 585 586 if (ctrl->status != LTESR_CC) 587 return NAND_STATUS_FAIL; 588 589 /* Use READ_STATUS command, but wait for the device to be ready */ 590 ctrl->use_mdr = 0; 591 out_be32(&lbc->fir, 592 (FIR_OP_CW0 << FIR_OP0_SHIFT) | 593 (FIR_OP_RBW << FIR_OP1_SHIFT)); 594 out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); 595 out_be32(&lbc->fbcr, 1); 596 set_addr(mtd, 0, 0, 0); 597 ctrl->read_bytes = 1; 598 599 fsl_elbc_run_command(mtd); 600 601 if (ctrl->status != LTESR_CC) 602 return NAND_STATUS_FAIL; 603 604 /* The chip always seems to report that it is 605 * write-protected, even when it is not. 606 */ 607 out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); 608 return fsl_elbc_read_byte(mtd); 609} 610 611static int fsl_elbc_read_page(struct mtd_info *mtd, struct nand_chip *chip, 612 uint8_t *buf, int oob_required, int page) 613{ 614 fsl_elbc_read_buf(mtd, buf, mtd->writesize); 615 fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); 616 617 if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) 618 mtd->ecc_stats.failed++; 619 620 return 0; 621} 622 623/* ECC will be calculated automatically, and errors will be detected in 624 * waitfunc. 625 */ 626static int fsl_elbc_write_page(struct mtd_info *mtd, struct nand_chip *chip, 627 const uint8_t *buf, int oob_required, 628 int page) 629{ 630 fsl_elbc_write_buf(mtd, buf, mtd->writesize); 631 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 632 633 return 0; 634} 635 636static struct fsl_elbc_ctrl *elbc_ctrl; 637 638/* ECC will be calculated automatically, and errors will be detected in 639 * waitfunc. 640 */ 641static int fsl_elbc_write_subpage(struct mtd_info *mtd, struct nand_chip *chip, 642 uint32_t offset, uint32_t data_len, 643 const uint8_t *buf, int oob_required, int page) 644{ 645 fsl_elbc_write_buf(mtd, buf, mtd->writesize); 646 fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); 647 648 return 0; 649} 650 651static void fsl_elbc_ctrl_init(void) 652{ 653 elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL); 654 if (!elbc_ctrl) 655 return; 656 657 elbc_ctrl->regs = LBC_BASE_ADDR; 658 659 /* clear event registers */ 660 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK); 661 out_be32(&elbc_ctrl->regs->lteatr, 0); 662 663 /* Enable interrupts for any detected events */ 664 out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK); 665 666 elbc_ctrl->read_bytes = 0; 667 elbc_ctrl->index = 0; 668 elbc_ctrl->addr = NULL; 669} 670 671static int fsl_elbc_chip_init(int devnum, u8 *addr, struct udevice *dev) 672{ 673 struct mtd_info *mtd; 674 struct nand_chip *nand; 675 struct fsl_elbc_mtd *priv; 676 uint32_t br = 0, or = 0; 677 int ret; 678 679 if (!elbc_ctrl) { 680 fsl_elbc_ctrl_init(); 681 if (!elbc_ctrl) 682 return -1; 683 } 684 685 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 686 if (!priv) 687 return -ENOMEM; 688 689 priv->ctrl = elbc_ctrl; 690 priv->vbase = addr; 691 692 /* Find which chip select it is connected to. It'd be nice 693 * if we could pass more than one datum to the NAND driver... 694 */ 695 for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { 696 phys_addr_t phys_addr = virt_to_phys(addr); 697 698 br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); 699 or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); 700 701 if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && 702 (br & or & BR_BA) == BR_PHYS_ADDR(phys_addr)) 703 break; 704 } 705 706 if (priv->bank >= MAX_BANKS) { 707 printf("fsl_elbc_nand: address did not match any " 708 "chip selects\n"); 709 kfree(priv); 710 return -ENODEV; 711 } 712 713 nand = &priv->chip; 714 mtd = nand_to_mtd(nand); 715 716 elbc_ctrl->chips[priv->bank] = priv; 717 718 /* fill in nand_chip structure */ 719 mtd->dev = dev; 720 nand->flash_node = dev ? dev_ofnode(dev) : ofnode_null(); 721 722 /* set up function call table */ 723 nand->read_byte = fsl_elbc_read_byte; 724 nand->write_buf = fsl_elbc_write_buf; 725 nand->read_buf = fsl_elbc_read_buf; 726 nand->select_chip = fsl_elbc_select_chip; 727 nand->cmdfunc = fsl_elbc_cmdfunc; 728 nand->waitfunc = fsl_elbc_wait; 729 730 /* set up nand options */ 731 nand->bbt_td = &bbt_main_descr; 732 nand->bbt_md = &bbt_mirror_descr; 733 734 /* set up nand options */ 735 nand->bbt_options = NAND_BBT_USE_FLASH; 736 737 nand->controller = &elbc_ctrl->controller; 738 nand_set_controller_data(nand, priv); 739 740 priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); 741 742 ret = nand_scan_ident(mtd, 1, NULL); 743 if (ret) 744 return ret; 745 746 /* If nand_scan_ident() has not selected ecc.mode, do it now */ 747 if (nand->ecc.mode == 0 748#if CONFIG_IS_ENABLED(OF_CONTROL) 749 && !ofnode_read_string(nand->flash_node, "nand-ecc-mode") 750#endif 751 ) { 752 /* If CS Base Register selects full hardware ECC then use it */ 753 if ((br & BR_DECC) == BR_DECC_CHK_GEN) { 754 nand->ecc.mode = NAND_ECC_HW; 755 nand->ecc.layout = (priv->fmr & FMR_ECCM) ? 756 &fsl_elbc_oob_sp_eccm1 : 757 &fsl_elbc_oob_sp_eccm0; 758 nand->ecc.size = 512; 759 nand->ecc.bytes = 3; 760 nand->ecc.steps = 1; 761 nand->ecc.strength = 1; 762 } else { 763 /* otherwise fall back to software ECC */ 764#if defined(CONFIG_NAND_ECC_BCH) 765 nand->ecc.mode = NAND_ECC_SOFT_BCH; 766#else 767 nand->ecc.mode = NAND_ECC_SOFT; 768#endif 769 } 770 } 771 772 if (nand->ecc.mode == NAND_ECC_HW) { 773 nand->ecc.read_page = fsl_elbc_read_page; 774 nand->ecc.write_page = fsl_elbc_write_page; 775 nand->ecc.write_subpage = fsl_elbc_write_subpage; 776 } 777 778 /* Large-page-specific setup */ 779 if (mtd->writesize == 2048) { 780 setbits_be32(&elbc_ctrl->regs->bank[priv->bank].or, 781 OR_FCM_PGS); 782 in_be32(&elbc_ctrl->regs->bank[priv->bank].or); 783 784 priv->page_size = 1; 785 nand->badblock_pattern = &largepage_memorybased; 786 787 /* 788 * Hardware expects small page has ECCM0, large page has 789 * ECCM1 when booting from NAND, and we follow that even 790 * when not booting from NAND. 791 */ 792 priv->fmr |= FMR_ECCM; 793 794 /* adjust ecc setup if needed */ 795 if (nand->ecc.mode == NAND_ECC_HW) { 796 nand->ecc.steps = 4; 797 nand->ecc.layout = (priv->fmr & FMR_ECCM) ? 798 &fsl_elbc_oob_lp_eccm1 : 799 &fsl_elbc_oob_lp_eccm0; 800 } 801 } else if (mtd->writesize == 512) { 802 clrbits_be32(&elbc_ctrl->regs->bank[priv->bank].or, 803 OR_FCM_PGS); 804 in_be32(&elbc_ctrl->regs->bank[priv->bank].or); 805 } else { 806 return -ENODEV; 807 } 808 809 ret = nand_scan_tail(mtd); 810 if (ret) 811 return ret; 812 813 ret = nand_register(devnum, mtd); 814 if (ret) 815 return ret; 816 817 return 0; 818} 819 820#ifndef CONFIG_NAND_FSL_ELBC_DT 821 822#ifndef CFG_SYS_NAND_BASE_LIST 823#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE } 824#endif 825 826static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] = 827 CFG_SYS_NAND_BASE_LIST; 828 829void board_nand_init(void) 830{ 831 int i; 832 833 for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) 834 fsl_elbc_chip_init(i, (u8 *)base_address[i], NULL); 835} 836 837#else 838 839static int fsl_elbc_nand_probe(struct udevice *dev) 840{ 841 return fsl_elbc_chip_init(0, dev_read_addr_ptr(dev), dev); 842} 843 844static const struct udevice_id fsl_elbc_nand_dt_ids[] = { 845 { .compatible = "fsl,elbc-fcm-nand", }, 846 {} 847}; 848 849U_BOOT_DRIVER(fsl_elbc_nand) = { 850 .name = "fsl_elbc_nand", 851 .id = UCLASS_MTD, 852 .of_match = fsl_elbc_nand_dt_ids, 853 .probe = fsl_elbc_nand_probe, 854}; 855 856void board_nand_init(void) 857{ 858 struct udevice *dev; 859 int ret; 860 861 ret = uclass_get_device_by_driver(UCLASS_MTD, DM_DRIVER_GET(fsl_elbc_nand), &dev); 862 if (ret && ret != -ENODEV) 863 printf("Failed to initialize fsl_elbc_nand NAND controller. (error %d)\n", ret); 864} 865#endif 866