Searched refs:cs_num (Results 1 - 21 of 21) sorted by relevance

/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_topology.c209 unsigned int cs_num = 0; local
222 cs_num++;
225 return cs_num;
320 unsigned int cs_num = mv_ddr_cs_num_get(); local
323 if (cs_num > 0 && cs_num <= MAX_CS_NUM)
324 rtt_park = tm->edata.mem_edata.rtt_park[cs_num - 1];
337 unsigned int cs_num = mv_ddr_cs_num_get(); local
340 if (cs_num > 0 && cs_num <
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H A Dddr3_init.c117 u32 cs_num; local
120 cs_num = mv_ddr_cs_num_get();
139 if (cs_num == 1) {
150 if (cs_num == 1) {
H A Dddr3_training_hw_algo.c45 u32 cs_num = 0, max_read_sample = 0, min_read_sample = 0x1f; local
63 for (cs_num = 0; cs_num < max_cs; cs_num++) {
64 read_sample[cs_num] = GET_RD_SAMPLE_DELAY(val, cs_num);
67 if (read_sample[cs_num] >= max_read_sample) {
68 if (read_sample[cs_num] == max_read_sample)
71 max_read_sample = read_sample[cs_num];
80 RL_PHY_REG(cs_num),
117 u32 cs_num; local
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H A Dddr3_training_ip_bist.h43 u32 offset, u32 cs_num, u32 pattern_addr_length);
45 u32 cs_num);
H A Dmv_ddr4_mpr_pda_if.h56 u32 if_id, u32 subphy_mask, u32 cs_num);
57 int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable);
H A Dddr3_training_ip_engine.h61 enum hws_ddr_cs cs_type, u32 cs_num,
75 enum hws_ddr_cs train_cs_type, u32 cs_num,
H A Dddr3_training.c12 #define CS_CBE_VALUE(cs_num) (cs_cbe_reg[cs_num])
300 int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) argument
307 if (tm->clk_enable & (1 << cs_num))
317 SDRAM_ADDR_CTRL_REG, (data << (cs_num * 4)),
318 0x3 << (cs_num * 4)));
325 (addr_hi << (2 + cs_num * 4)),
326 0x3 << (2 + cs_num * 4)));
332 data_high << (20 + cs_num), 1 << (20 + cs_num)));
365 u32 cs_num; local
1241 u32 cs_num; local
1891 u32 if_id, bus_num, cs_bitmask, data_val, cs_num; local
3002 unsigned int cs_num = mv_ddr_cs_num_get(); local
3017 unsigned int cs_num = mv_ddr_cs_num_get(); local
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H A Dddr3_training_pbs.c48 u32 pup = 0, bit = 0, if_id = 0, all_lock = 0, cs_num = 0; local
83 pbs_pattern, search_edge, CS_SINGLE, cs_num,
214 search_edge, CS_SINGLE, cs_num,
397 CS_SINGLE, cs_num, train_status);
526 cs_num, train_status);
623 search_edge, CS_SINGLE, cs_num,
940 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode) argument
944 PBS_RX_PHY_REG(cs_num, 0) :
945 PBS_TX_PHY_REG(cs_num , 0);
950 (pbs_mode == PBS_RX_MODE) ? "Rx" : "Tx", cs_num);
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H A Dddr3_training_bist.c26 u32 offset, u32 cs_num, u32 pattern_addr_length)
55 rd_mode, cs_num, addr_stress_jump, duration);
119 u32 cs_num)
129 hws_ddr3_cs_base_adr_calc(i, cs_num, &win_base);
135 cs_num, 15);
146 cs_num, 15);
20 ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern, enum hws_access_type access_type, u32 if_num, enum hws_dir dir, enum hws_stress_jump addr_stress_jump, enum hws_pattern_duration duration, enum hws_bist_operation oper_type, u32 offset, u32 cs_num, u32 pattern_addr_length) argument
118 hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result, u32 cs_num) argument
H A Dddr3_training_ip.h129 u8 cs_num; member in struct:cs_element
H A Dddr3_training_ip_engine.c482 enum hws_ddr_cs cs_type, u32 cs_num,
530 ODPG_DATA_CTRL_REG, 0x3 | cs_num << 26,
769 u32 delay_between_burst, u32 rd_mode, u32 cs_num,
777 (rx_phases << 21) | (rd_mode << 25) | (cs_num << 26) |
1116 enum hws_ddr_cs train_cs_type, u32 cs_num,
1167 ("dev_num %d, access_type %d, if_id %d, pup_access_type %d,pup_num %d, result_type %d, control_element %d search_dir_id %d, direction %d, interface_mask %d,init_value_used %d, num_iter %d, pattern %d, edge_comp_used %d, train_cs_type %d, cs_num %d\n",
1171 pattern, edge_comp_used, train_cs_type, cs_num));
1178 cs_num, train_status);
1190 cs_num = 0;
1253 enum hws_ddr_cs train_cs_type, u32 cs_num,
473 ddr3_tip_ip_training(u32 dev_num, enum hws_access_type access_type, u32 interface_num, enum hws_access_type pup_access_type, u32 pup_num, enum hws_training_result result_type, enum hws_control_element control_element, enum hws_search_dir search_dir, enum hws_dir direction, u32 interface_mask, u32 init_value, u32 num_iter, enum hws_pattern pattern, enum hws_edge_compare edge_comp, enum hws_ddr_cs cs_type, u32 cs_num, enum hws_training_ip_stat *train_status) argument
766 ddr3_tip_configure_odpg(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_dir direction, u32 tx_phases, u32 tx_burst_size, u32 rx_phases, u32 delay_between_burst, u32 rd_mode, u32 cs_num, u32 addr_stress_jump, u32 single_pattern) argument
1103 ddr3_tip_ip_training_wrapper_int(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_access_type pup_access_type, u32 pup_num, u32 bit_num, enum hws_training_result result_type, enum hws_control_element control_element, enum hws_search_dir search_dir, enum hws_dir direction, u32 interface_mask, u32 init_value_l2h, u32 init_value_h2l, u32 num_iter, enum hws_pattern pattern, enum hws_edge_compare edge_comp, enum hws_ddr_cs train_cs_type, u32 cs_num, enum hws_training_ip_stat *train_status) argument
1242 ddr3_tip_ip_training_wrapper(u32 dev_num, enum hws_access_type access_type, u32 if_id, enum hws_access_type pup_access_type, u32 pup_num, enum hws_training_result result_type, enum hws_control_element control_element, enum hws_search_dir search_dir, enum hws_dir direction, u32 interface_mask, u32 init_value_l2h, u32 init_value_h2l, u32 num_iter, enum hws_pattern pattern, enum hws_edge_compare edge_comp, enum hws_ddr_cs train_cs_type, u32 cs_num, enum hws_training_ip_stat *train_status) argument
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H A Dddr3_training_ip_prv_if.h78 enum hws_bist_operation oper_type, u32 offset, u32 cs_num,
H A Dddr3_training_ip_flow.h116 u32 delay_between_burst, u32 rd_mode, u32 cs_num,
H A Dmv_ddr4_mpr_pda_if.c573 u32 if_id, u32 subphy_mask, u32 cs_num)
585 val = (cs_num << 26) | (0x1 << 25) | (0x3 << 11) | (0x3 << 5) | 0x1;
629 int mv_ddr4_pda_ctrl(u8 dev_num, u8 if_id, u8 cs_num, int enable) argument
650 if (cs_num == 0)
572 mv_ddr4_pda_pattern_odpg_load(u32 dev_num, enum hws_access_type access_type, u32 if_id, u32 subphy_mask, u32 cs_num) argument
H A Dddr3_init.h189 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
/u-boot/drivers/spi/
H A Dmscc_bb_spi.c23 int cs_num; member in struct:mscc_bb_priv
38 priv->cs_num = cs;
70 debug("Activated CS%d\n", priv->cs_num);
100 debug("Deactivated CS%d\n", priv->cs_num);
/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_sdram.c494 u32 chan, byte_count, cs_num, byte; local
510 cs_num = (src / (1 + SDRAM_CS_SIZE));
512 ((cs_num << 1) | (1 << 0)));
517 cs_num = (dst / (1 + SDRAM_CS_SIZE));
519 ((cs_num << 25) | (1 << 24)));
H A Dddr3_spd.c593 u32 cs, cl, cs_num, cs_ena; local
650 cs_num = 0;
652 cs_num = ddr3_get_cs_num_from_reg();
656 cs_num += dimm_info[dimm].num_of_module_ranks;
658 if (cs_num > MAX_CS) {
699 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Number of CS = ", cs_num, 1);
1083 if (cs_num > 1)
/u-boot/arch/arm/mach-sunxi/
H A Ddram_suniv.c46 u32 cs_num; /* dram chip count 1: one chip 2: two chip */ member in struct:dram_para
60 .cs_num = 1,
134 ((para->cs_num >> 1) << 4) |
/u-boot/drivers/memory/
H A Dti-gpmc.c35 u32 cs_num; member in struct:ti_gpmc
1155 gpmc->cs_num = val;
/u-boot/drivers/ram/rockchip/
H A Dsdram_rv1126.c1969 void __iomem *phy_base, u8 cs_num)
1973 result->cs_num = cs_num;
2011 struct fsp_rw_trn_result *result, u8 cs_num,
2020 for (cs = 0; cs < cs_num; cs++) {
2136 rw_trn_result.cs_num, (u8)(min_val * (-1)),
2153 rw_trn_result.cs_num, (u8)(min_val * (-1)),
1968 init_rw_trn_result_struct(struct rw_trn_result *result, void __iomem *phy_base, u8 cs_num) argument
2010 save_rw_trn_deskew(void __iomem *phy_base, struct fsp_rw_trn_result *result, u8 cs_num, int min_val, bool rw) argument

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