Searched refs:clocks (Results 1 - 25 of 45) sorted by relevance

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/u-boot/drivers/usb/host/
H A Dohci-da8xx.c21 struct clk *clocks; /* clock list */ member in struct:da8xx_ohci
98 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
105 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
107 if (!priv->clocks)
111 err = clk_get_by_index(dev, i, &priv->clocks[i]);
115 err = clk_enable(&priv->clocks[i]);
141 ret = clk_release_all(priv->clocks, priv->clock_count);
143 dev_err(dev, "failed to disable all clocks\n");
161 return clk_release_all(priv->clocks, priv->clock_count);
H A Dohci-generic.c19 struct clk_bulk clocks; /* clock list */ member in struct:generic_ohci
30 ret = clk_get_bulk(dev, &priv->clocks);
32 dev_err(dev, "Failed to get clocks (ret=%d)\n", ret);
36 err = clk_enable_bulk(&priv->clocks);
38 dev_err(dev, "Failed to enable clocks (err=%d)\n", err);
74 ret = clk_release_bulk(&priv->clocks);
76 dev_err(dev, "failed to release clocks (ret=%d)\n", ret);
98 return clk_release_bulk(&priv->clocks);
H A Dehci-generic.c26 struct clk_bulk clocks; member in struct:generic_ehci
70 ret = clk_get_bulk(dev, &priv->clocks);
72 dev_err(dev, "Failed to get clocks (ret=%d)\n", ret);
76 err = clk_enable_bulk(&priv->clocks);
78 dev_err(dev, "Failed to enable clocks (err=%d)\n", err);
127 ret = clk_release_bulk(&priv->clocks);
129 dev_err(dev, "failed to release clocks (ret=%d)\n", ret);
155 return clk_release_bulk(&priv->clocks);
/u-boot/drivers/phy/
H A Dmt7620-usb-phy.c19 struct clk_bulk clocks; member in struct:mt7620_usb_phy
31 clk_enable_bulk(&phy->clocks);
51 clk_disable_bulk(&phy->clocks);
78 ret = clk_get_bulk(dev, &phy->clocks);
80 dev_err(dev, "mt7620_usbphy: failed to get clocks\n");
/u-boot/drivers/bus/
H A Dti-sysc.c23 struct clk clocks[TI_SYSC_MAX_CLOCKS]; member in struct:ti_sysc_priv
57 err = clk_get_by_name(dev, name, &priv->clocks[index]);
74 err = clk_release_all(priv->clocks, priv->clocks_count);
76 dev_err(dev, "failed to release all clocks\n");
103 err = clk_disable(&priv->clocks[i]);
120 err = clk_enable(&priv->clocks[i]);
/u-boot/test/dm/
H A Dof_platdata.c189 ut_assertok(device_get_by_ofplat_idx(plat->clocks[0].idx, &clk));
192 ut_assertok(device_get_by_ofplat_idx(plat->clocks[1].idx, &clk));
194 ut_asserteq(1, plat->clocks[1].arg[0]);
196 ut_assertok(device_get_by_ofplat_idx(plat->clocks[2].idx, &clk));
198 ut_asserteq(0, plat->clocks[2].arg[0]);
200 ut_assertok(device_get_by_ofplat_idx(plat->clocks[3].idx, &clk));
202 ut_asserteq(3, plat->clocks[3].arg[0]);
204 ut_assertok(device_get_by_ofplat_idx(plat->clocks[4].idx, &clk));
206 ut_asserteq(2, plat->clocks[4].arg[0]);
227 /* Test clocks wit
[all...]
/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A Dclk-bcm281xx.c35 * Reference clocks
38 /* Declare a list of reference clocks */
142 /* * Master CCU clocks */
145 .clocks = CLOCKS("ref_crystal",
157 .clocks = CLOCKS("ref_crystal",
169 .clocks = CLOCKS("ref_crystal",
181 .clocks = CLOCKS("ref_crystal",
192 .clocks = CLOCKS("ref_32k"),
197 .clocks = CLOCKS("ref_32k"),
202 .clocks
[all...]
H A Dclk-core.c103 * supported by u-boot which includes all clocks
176 for (clock = cd->clocks; *clock; clock++, i++) {
222 * For peri clocks that don't have a selector, the single
234 clock = cd->clocks;
/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A Dclk-bcm235xx.c35 * Reference clocks
38 /* Declare a list of reference clocks */
142 /* * Master CCU clocks */
145 .clocks = CLOCKS("ref_crystal",
157 .clocks = CLOCKS("ref_crystal",
169 .clocks = CLOCKS("ref_crystal",
181 .clocks = CLOCKS("ref_crystal",
192 .clocks = CLOCKS("ref_32k"),
197 .clocks = CLOCKS("ref_32k"),
202 .clocks
[all...]
H A Dclk-core.c103 * supported by u-boot which includes all clocks
176 for (clock = cd->clocks; *clock; clock++, i++) {
222 * For peri clocks that don't have a selector, the single
234 clock = cd->clocks;
/u-boot/arch/arm/mach-omap2/
H A DMakefile24 obj-y += clocks-common.o
/u-boot/drivers/clk/renesas/
H A Dr9a06g032-clocks.c617 * These are not hardware clocks, but are needed to handle the special
698 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
706 parent_rate = clk_get_rate(&clocks->mclk);
717 static void clk_rdesc_set(struct r9a06g032_priv *clocks, argument
729 regmap_update_bits(clocks->regmap, reg, mask, val);
732 static int clk_rdesc_get(struct r9a06g032_priv *clocks, argument
739 regmap_read(clocks->regmap, reg, &val);
750 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
758 clk_rdesc_set(clocks, g->reset, on);
768 struct r9a06g032_priv *clocks local
832 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
848 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
901 r9a06g032_clk_dualgate_setenable(struct r9a06g032_priv *clocks, const struct r9a06g032_clkdesc *desc, int enable) argument
922 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
930 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
938 struct r9a06g032_priv *clocks = dev_get_priv(clk->dev); local
[all...]
H A DMakefile26 obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o
/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager.c112 clocks, CONFIG_SYS_MAXARGS, 1, do_showclocks,
113 "display clocks",
/u-boot/drivers/net/
H A Ddwc_eth_qos_qcom.c389 struct clk_bulk clocks; local
392 ret = clk_get_bulk(dev, &clocks);
396 ret = clk_enable_bulk(&clocks);
408 struct clk_bulk clocks; local
411 ret = clk_get_bulk(dev, &clocks);
415 ret = clk_disable_bulk(&clocks);
H A Ddesignware.h240 struct clk *clocks; /* clock list */ member in struct:dw_eth_dev
H A Ddesignware.c706 clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells",
709 priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
711 if (!priv->clocks)
715 err = clk_get_by_index(dev, i, &priv->clocks[i]);
719 err = clk_enable(&priv->clocks[i]);
801 ret = clk_release_all(priv->clocks, priv->clock_count);
803 pr_err("failed to disable all clocks\n");
818 return clk_release_all(priv->clocks, priv->clock_count);
/u-boot/drivers/mmc/
H A Dmeson_gx_mmc.c264 struct clk_bulk clocks; local
268 /* Enable the clocks feeding the MMC controller */
269 ret = clk_get_bulk(dev, &clocks);
273 ret = clk_enable_bulk(&clocks);
H A Dftsdc010_mci.c42 struct phandle_2_cell clocks[4]; member in struct:ftsdc010
436 ret = clk_get_by_phandle(dev, dtplat->clocks, &priv->clk);
/u-boot/drivers/timer/
H A Ddw-apb-timer.c59 ret = clk_get_by_phandle(dev, &dtplat->clocks[0], &clk);
/u-boot/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c121 struct clk clocks; member in struct:sun4i_usb_phy_plat
263 ret = clk_enable(&usb_phy->clocks);
281 ret = clk_enable(&phy2->clocks);
377 ret = clk_disable(&usb_phy->clocks);
534 ret = clk_get_by_name(dev, name, &phy->clocks);
/u-boot/drivers/video/meson/
H A Dmeson_dw_hdmi.c300 /* Enable clocks */
386 struct clk_bulk clocks; local
435 ret = clk_get_bulk(dev, &clocks);
439 ret = clk_enable_bulk(&clocks);
443 /* Enable clocks */
/u-boot/drivers/video/sunxi/
H A Dsunxi_dw_hdmi.c27 struct clk_bulk clocks; member in struct:sunxi_dw_hdmi_priv
355 ret = clk_enable_bulk(&priv->clocks);
390 ret = clk_get_bulk(dev, &priv->clocks);
/u-boot/drivers/clk/meson/
H A Da1.c94 * @num_clocks: Number of clocks
95 * @clocks: Array of clock descriptions
100 const struct meson_clk_info **clocks; member in struct:meson_clk_data
170 /* A1 peripherals clocks */
267 /* A1 PLL clocks */
316 info = data->clocks[id];
618 .clocks = meson_clocks,
623 .clocks = meson_pll_clocks,
/u-boot/arch/arm/cpu/arm926ejs/mxs/
H A Dmxs.c216 /* Turn on ENET clocks */
296 clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
297 "display clocks",

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