1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * (C) Copyright 2023 SberDevices, Inc. 4 * Author: Igor Prusov <ivprusov@salutedevices.com> 5 */ 6 7#include <common.h> 8#include <clk-uclass.h> 9#include <dm.h> 10#include <regmap.h> 11#include <asm/arch/clock-a1.h> 12#include <dt-bindings/clock/amlogic,a1-pll-clkc.h> 13#include <dt-bindings/clock/amlogic,a1-peripherals-clkc.h> 14#include "clk_meson.h" 15 16/* 17 * This driver supports both PLL and peripherals clock sources. 18 * Following operations are supported: 19 * - calculating clock frequency on a limited tree 20 * - reading muxes and dividers 21 * - enabling/disabling gates without propagation 22 * - reparenting without rate propagation, only on muxes 23 * - setting rates with limited reparenting, only on dividers with mux parent 24 */ 25 26#define NR_CLKS 154 27#define NR_PLL_CLKS 11 28 29/* External clock IDs. Those should not overlap with regular IDs */ 30#define EXTERNAL_XTAL (NR_CLKS + 0) 31#define EXTERNAL_FCLK_DIV2 (NR_CLKS + 1) 32#define EXTERNAL_FCLK_DIV3 (NR_CLKS + 2) 33#define EXTERNAL_FCLK_DIV5 (NR_CLKS + 3) 34#define EXTERNAL_FCLK_DIV7 (NR_CLKS + 4) 35 36#define EXTERNAL_FIXPLL_IN (NR_PLL_CLKS + 1) 37 38#define SET_PARM_VALUE(_priv, _parm, _val) \ 39 regmap_update_bits((_priv)->map, (_parm)->reg_off, \ 40 SETPMASK((_parm)->width, (_parm)->shift), \ 41 (_val) << (_parm)->shift) 42 43#define GET_PARM_VALUE(_priv, _parm) \ 44({ \ 45 uint _reg; \ 46 regmap_read((_priv)->map, (_parm)->reg_off, &_reg); \ 47 PARM_GET((_parm)->width, (_parm)->shift, _reg); \ 48}) 49 50struct meson_clk { 51 struct regmap *map; 52}; 53 54/** 55 * enum meson_clk_type - The type of clock 56 * @MESON_CLK_ANY: Special value that matches any clock type 57 * @MESON_CLK_GATE: This clock is a gate 58 * @MESON_CLK_MUX: This clock is a multiplexer 59 * @MESON_CLK_DIV: This clock is a configurable divider 60 * @MESON_CLK_FIXED_DIV: This clock is a configurable divider 61 * @MESON_CLK_EXTERNAL: This is an external clock from different clock provider 62 * @MESON_CLK_PLL: This is a PLL 63 */ 64enum meson_clk_type { 65 MESON_CLK_ANY = 0, 66 MESON_CLK_GATE, 67 MESON_CLK_MUX, 68 MESON_CLK_DIV, 69 MESON_CLK_FIXED_DIV, 70 MESON_CLK_EXTERNAL, 71 MESON_CLK_PLL, 72}; 73 74/** 75 * struct meson_clk_info - The parameters defining a clock 76 * @name: Name of the clock 77 * @parm: Register bits description for muxes and dividers 78 * @div: Fixed divider value 79 * @parents: List of parent clock IDs 80 * @type: Clock type 81 */ 82struct meson_clk_info { 83 const char *name; 84 union { 85 const struct parm *parm; 86 u8 div; 87 }; 88 const unsigned int *parents; 89 const enum meson_clk_type type; 90}; 91 92/** 93 * struct meson_clk_data - Clocks supported by clock provider 94 * @num_clocks: Number of clocks 95 * @clocks: Array of clock descriptions 96 * 97 */ 98struct meson_clk_data { 99 const u8 num_clocks; 100 const struct meson_clk_info **clocks; 101}; 102 103/* Clock description initialization macros */ 104 105/* A multiplexer */ 106#define CLK_MUX(_name, _reg, _shift, _width, ...) \ 107 (&(struct meson_clk_info){ \ 108 .parents = (const unsigned int[])__VA_ARGS__, \ 109 .parm = &(struct parm) { \ 110 .reg_off = (_reg), \ 111 .shift = (_shift), \ 112 .width = (_width), \ 113 }, \ 114 .name = (_name), \ 115 .type = MESON_CLK_MUX, \ 116 }) 117 118/* A divider with an integral divisor */ 119#define CLK_DIV(_name, _reg, _shift, _width, _parent) \ 120 (&(struct meson_clk_info){ \ 121 .parents = (const unsigned int[]) { (_parent) }, \ 122 .parm = &(struct parm) { \ 123 .reg_off = (_reg), \ 124 .shift = (_shift), \ 125 .width = (_width), \ 126 }, \ 127 .name = (_name), \ 128 .type = MESON_CLK_DIV, \ 129 }) 130 131/* A fixed divider */ 132#define CLK_DIV_FIXED(_name, _div, _parent) \ 133 (&(struct meson_clk_info){ \ 134 .parents = (const unsigned int[]) { (_parent) }, \ 135 .div = (_div), \ 136 .name = (_name), \ 137 .type = MESON_CLK_FIXED_DIV, \ 138 }) 139 140/* An external clock */ 141#define CLK_EXTERNAL(_name) \ 142 (&(struct meson_clk_info){ \ 143 .name = (_name), \ 144 .parents = (const unsigned int[]) { -ENOENT }, \ 145 .type = MESON_CLK_EXTERNAL, \ 146 }) 147 148/* A clock gate */ 149#define CLK_GATE(_name, _reg, _shift, _parent) \ 150 (&(struct meson_clk_info){ \ 151 .parents = (const unsigned int[]) { (_parent) }, \ 152 .parm = &(struct parm) { \ 153 .reg_off = (_reg), \ 154 .shift = (_shift), \ 155 .width = 1, \ 156 }, \ 157 .name = (_name), \ 158 .type = MESON_CLK_GATE, \ 159 }) 160 161/* A PLL clock */ 162#define CLK_PLL(_name, _parent, ...) \ 163 (&(struct meson_clk_info){ \ 164 .name = (_name), \ 165 .parents = (const unsigned int[]) { (_parent) }, \ 166 .parm = (const struct parm[])__VA_ARGS__, \ 167 .type = MESON_CLK_PLL, \ 168 }) 169 170/* A1 peripherals clocks */ 171static const struct meson_clk_info *meson_clocks[] = { 172 [CLKID_SPIFC_SEL] = CLK_MUX("spifc_sel", A1_SPIFC_CLK_CTRL, 9, 2, { 173 EXTERNAL_FCLK_DIV2, 174 EXTERNAL_FCLK_DIV3, 175 EXTERNAL_FCLK_DIV5, 176 -ENOENT, 177 }), 178 [CLKID_SPIFC_SEL2] = CLK_MUX("spifc_sel2", A1_SPIFC_CLK_CTRL, 15, 1, { 179 CLKID_SPIFC_DIV, 180 EXTERNAL_XTAL, 181 }), 182 [CLKID_USB_BUS_SEL] = CLK_MUX("usb_bus_sel", A1_USB_BUSCLK_CTRL, 9, 2, { 183 -ENOENT, 184 CLKID_SYS, 185 EXTERNAL_FCLK_DIV3, 186 EXTERNAL_FCLK_DIV5, 187 }), 188 [CLKID_SYS] = CLK_MUX("sys", A1_SYS_CLK_CTRL0, 31, 1, { 189 CLKID_SYS_A, 190 CLKID_SYS_B, 191 }), 192 [CLKID_SYS_A_SEL] = CLK_MUX("sys_a_sel", A1_SYS_CLK_CTRL0, 10, 3, { 193 -ENOENT, 194 EXTERNAL_FCLK_DIV2, 195 EXTERNAL_FCLK_DIV3, 196 EXTERNAL_FCLK_DIV5, 197 -ENOENT, 198 -ENOENT, 199 -ENOENT, 200 -ENOENT, 201 }), 202 [CLKID_SYS_B_SEL] = CLK_MUX("sys_b_sel", A1_SYS_CLK_CTRL0, 26, 3, { 203 -ENOENT, 204 EXTERNAL_FCLK_DIV2, 205 EXTERNAL_FCLK_DIV3, 206 EXTERNAL_FCLK_DIV5, 207 -ENOENT, 208 -ENOENT, 209 -ENOENT, 210 -ENOENT, 211 }), 212 213 [CLKID_SPIFC_DIV] = CLK_DIV("spifc_div", A1_SPIFC_CLK_CTRL, 0, 8, 214 CLKID_SPIFC_SEL 215 ), 216 [CLKID_USB_BUS_DIV] = CLK_DIV("usb_bus_div", A1_USB_BUSCLK_CTRL, 0, 8, 217 CLKID_USB_BUS_SEL 218 ), 219 [CLKID_SYS_A_DIV] = CLK_DIV("sys_a_div", A1_SYS_CLK_CTRL0, 0, 10, 220 CLKID_SYS_A_SEL 221 ), 222 [CLKID_SYS_B_DIV] = CLK_DIV("sys_b_div", A1_SYS_CLK_CTRL0, 16, 10, 223 CLKID_SYS_B_SEL 224 ), 225 226 [CLKID_SPIFC] = CLK_GATE("spifc", A1_SPIFC_CLK_CTRL, 8, 227 CLKID_SPIFC_SEL2 228 ), 229 [CLKID_USB_BUS] = CLK_GATE("usb_bus", A1_USB_BUSCLK_CTRL, 8, 230 CLKID_USB_BUS_DIV 231 ), 232 [CLKID_SYS_A] = CLK_GATE("sys_a", A1_SYS_CLK_CTRL0, 13, 233 CLKID_SYS_A_DIV 234 ), 235 [CLKID_SYS_B] = CLK_GATE("sys_b", A1_SYS_CLK_CTRL0, 29, 236 CLKID_SYS_B_DIV 237 ), 238 [CLKID_FIXPLL_IN] = CLK_GATE("fixpll_in", A1_SYS_OSCIN_CTRL, 1, 239 EXTERNAL_XTAL 240 ), 241 [CLKID_USB_PHY_IN] = CLK_GATE("usb_phy_in", A1_SYS_OSCIN_CTRL, 2, 242 EXTERNAL_XTAL 243 ), 244 [CLKID_USB_CTRL_IN] = CLK_GATE("usb_ctrl_in", A1_SYS_OSCIN_CTRL, 3, 245 EXTERNAL_XTAL 246 ), 247 [CLKID_USB_CTRL] = CLK_GATE("usb_ctrl", A1_SYS_CLK_EN0, 28, 248 CLKID_SYS 249 ), 250 [CLKID_USB_PHY] = CLK_GATE("usb_phy", A1_SYS_CLK_EN0, 27, 251 CLKID_SYS 252 ), 253 [CLKID_SARADC] = CLK_GATE("saradc", A1_SAR_ADC_CLK_CTR, 8, 254 -ENOENT 255 ), 256 [CLKID_SARADC_EN] = CLK_GATE("saradc_en", A1_SYS_CLK_EN0, 13, 257 CLKID_SYS 258 ), 259 260 [EXTERNAL_XTAL] = CLK_EXTERNAL("xtal"), 261 [EXTERNAL_FCLK_DIV2] = CLK_EXTERNAL("fclk_div2"), 262 [EXTERNAL_FCLK_DIV3] = CLK_EXTERNAL("fclk_div3"), 263 [EXTERNAL_FCLK_DIV5] = CLK_EXTERNAL("fclk_div5"), 264 [EXTERNAL_FCLK_DIV7] = CLK_EXTERNAL("fclk_div7"), 265}; 266 267/* A1 PLL clocks */ 268static const struct meson_clk_info *meson_pll_clocks[] = { 269 [EXTERNAL_FIXPLL_IN] = CLK_EXTERNAL("fixpll_in"), 270 271 [CLKID_FIXED_PLL_DCO] = CLK_PLL("fixed_pll_dco", EXTERNAL_FIXPLL_IN, { 272 {A1_ANACTRL_FIXPLL_CTRL0, 0, 8}, 273 {A1_ANACTRL_FIXPLL_CTRL0, 10, 5}, 274 }), 275 276 [CLKID_FCLK_DIV2_DIV] = CLK_DIV_FIXED("fclk_div2_div", 2, 277 CLKID_FIXED_PLL 278 ), 279 [CLKID_FCLK_DIV3_DIV] = CLK_DIV_FIXED("fclk_div3_div", 3, 280 CLKID_FIXED_PLL 281 ), 282 [CLKID_FCLK_DIV5_DIV] = CLK_DIV_FIXED("fclk_div5_div", 5, 283 CLKID_FIXED_PLL 284 ), 285 [CLKID_FCLK_DIV7_DIV] = CLK_DIV_FIXED("fclk_div7_div", 7, 286 CLKID_FIXED_PLL 287 ), 288 289 [CLKID_FIXED_PLL] = CLK_GATE("fixed_pll", A1_ANACTRL_FIXPLL_CTRL0, 20, 290 CLKID_FIXED_PLL_DCO 291 ), 292 [CLKID_FCLK_DIV2] = CLK_GATE("fclk_div2", A1_ANACTRL_FIXPLL_CTRL0, 21, 293 CLKID_FCLK_DIV2_DIV 294 ), 295 [CLKID_FCLK_DIV3] = CLK_GATE("fclk_div3", A1_ANACTRL_FIXPLL_CTRL0, 22, 296 CLKID_FCLK_DIV3_DIV 297 ), 298 [CLKID_FCLK_DIV5] = CLK_GATE("fclk_div5", A1_ANACTRL_FIXPLL_CTRL0, 23, 299 CLKID_FCLK_DIV5_DIV 300 ), 301 [CLKID_FCLK_DIV7] = CLK_GATE("fclk_div7", A1_ANACTRL_FIXPLL_CTRL0, 24, 302 CLKID_FCLK_DIV7_DIV 303 ), 304}; 305 306static const struct meson_clk_info *meson_clk_get_info(struct clk *clk, ulong id, 307 enum meson_clk_type type) 308{ 309 struct meson_clk_data *data; 310 const struct meson_clk_info *info; 311 312 data = (struct meson_clk_data *)dev_get_driver_data(clk->dev); 313 if (id >= data->num_clocks) 314 return ERR_PTR(-EINVAL); 315 316 info = data->clocks[id]; 317 if (!info) 318 return ERR_PTR(-ENOENT); 319 320 if (type != MESON_CLK_ANY && type != info->type) 321 return ERR_PTR(-EINVAL); 322 323 return info; 324} 325 326static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id); 327 328static int meson_set_gate(struct clk *clk, bool on) 329{ 330 struct meson_clk *priv = dev_get_priv(clk->dev); 331 const struct meson_clk_info *info; 332 333 debug("%s: %sabling %lu\n", __func__, on ? "en" : "dis", clk->id); 334 335 info = meson_clk_get_info(clk, clk->id, MESON_CLK_ANY); 336 if (IS_ERR(info)) 337 return PTR_ERR(info); 338 339 SET_PARM_VALUE(priv, info->parm, on); 340 341 return 0; 342} 343 344static int meson_clk_enable(struct clk *clk) 345{ 346 return meson_set_gate(clk, true); 347} 348 349static int meson_clk_disable(struct clk *clk) 350{ 351 return meson_set_gate(clk, false); 352} 353 354static ulong meson_div_get_rate(struct clk *clk, unsigned long id) 355{ 356 struct meson_clk *priv = dev_get_priv(clk->dev); 357 u16 n; 358 ulong rate; 359 const struct meson_clk_info *info; 360 361 info = meson_clk_get_info(clk, id, MESON_CLK_DIV); 362 if (IS_ERR(info)) 363 return PTR_ERR(info); 364 365 /* Actual divider value is (field value + 1), hence the increment */ 366 n = GET_PARM_VALUE(priv, info->parm) + 1; 367 368 rate = meson_clk_get_rate_by_id(clk, info->parents[0]); 369 370 return rate / n; 371} 372 373static int meson_clk_get_parent(struct clk *clk, unsigned long id) 374{ 375 uint reg = 0; 376 struct meson_clk *priv = dev_get_priv(clk->dev); 377 const struct meson_clk_info *info; 378 379 info = meson_clk_get_info(clk, id, MESON_CLK_ANY); 380 if (IS_ERR(info)) 381 return PTR_ERR(info); 382 383 /* For muxes we read currently selected parent from register, 384 * for other types there is always only one element in parents array. 385 */ 386 if (info->type == MESON_CLK_MUX) { 387 reg = GET_PARM_VALUE(priv, info->parm); 388 if (IS_ERR_VALUE(reg)) 389 return reg; 390 } 391 392 return info->parents[reg]; 393} 394 395static ulong meson_pll_get_rate(struct clk *clk, unsigned long id) 396{ 397 struct meson_clk *priv = dev_get_priv(clk->dev); 398 const struct meson_clk_info *info; 399 const struct parm *pm, *pn; 400 ulong parent_rate_mhz; 401 unsigned int parent; 402 u16 n, m; 403 404 info = meson_clk_get_info(clk, id, MESON_CLK_ANY); 405 if (IS_ERR(info)) 406 return PTR_ERR(info); 407 408 pm = &info->parm[0]; 409 pn = &info->parm[1]; 410 411 n = GET_PARM_VALUE(priv, pn); 412 m = GET_PARM_VALUE(priv, pm); 413 414 if (n == 0) 415 return -EINVAL; 416 417 parent = info->parents[0]; 418 parent_rate_mhz = meson_clk_get_rate_by_id(clk, parent) / 1000000; 419 420 return parent_rate_mhz * m / n * 1000000; 421} 422 423static ulong meson_clk_get_rate_by_id(struct clk *clk, unsigned long id) 424{ 425 ulong rate, parent; 426 const struct meson_clk_info *info; 427 428 if (IS_ERR_VALUE(id)) 429 return id; 430 431 info = meson_clk_get_info(clk, id, MESON_CLK_ANY); 432 if (IS_ERR(info)) 433 return PTR_ERR(info); 434 435 switch (info->type) { 436 case MESON_CLK_PLL: 437 rate = meson_pll_get_rate(clk, id); 438 break; 439 case MESON_CLK_GATE: 440 case MESON_CLK_MUX: 441 parent = meson_clk_get_parent(clk, id); 442 rate = meson_clk_get_rate_by_id(clk, parent); 443 break; 444 case MESON_CLK_DIV: 445 rate = meson_div_get_rate(clk, id); 446 break; 447 case MESON_CLK_FIXED_DIV: 448 parent = meson_clk_get_parent(clk, id); 449 rate = meson_clk_get_rate_by_id(clk, parent) / info->div; 450 break; 451 case MESON_CLK_EXTERNAL: { 452 int ret; 453 struct clk external_clk; 454 455 ret = clk_get_by_name(clk->dev, info->name, &external_clk); 456 if (ret) 457 return ret; 458 459 rate = clk_get_rate(&external_clk); 460 break; 461 } 462 default: 463 rate = -EINVAL; 464 break; 465 } 466 467 return rate; 468} 469 470static ulong meson_clk_get_rate(struct clk *clk) 471{ 472 return meson_clk_get_rate_by_id(clk, clk->id); 473} 474 475/* This implements rate propagation for dividers placed after multiplexer: 476 * ---------|\ 477 * ..... | |---DIV-- 478 * ---------|/ 479 */ 480static ulong meson_composite_set_rate(struct clk *clk, ulong id, ulong rate) 481{ 482 unsigned int i, best_div_val; 483 unsigned long best_delta, best_parent; 484 const struct meson_clk_info *div; 485 const struct meson_clk_info *mux; 486 struct meson_clk *priv = dev_get_priv(clk->dev); 487 488 div = meson_clk_get_info(clk, id, MESON_CLK_DIV); 489 if (IS_ERR(div)) 490 return PTR_ERR(div); 491 492 mux = meson_clk_get_info(clk, div->parents[0], MESON_CLK_MUX); 493 if (IS_ERR(mux)) 494 return PTR_ERR(mux); 495 496 best_parent = -EINVAL; 497 best_delta = ULONG_MAX; 498 for (i = 0; i < (1 << mux->parm->width); i++) { 499 unsigned long parent_rate, delta; 500 unsigned int div_val; 501 502 parent_rate = meson_clk_get_rate_by_id(clk, mux->parents[i]); 503 if (IS_ERR_VALUE(parent_rate)) 504 continue; 505 506 /* If overflow, try to use max divider value */ 507 div_val = min(DIV_ROUND_CLOSEST(parent_rate, rate), 508 (1UL << div->parm->width)); 509 510 delta = abs(rate - (parent_rate / div_val)); 511 if (delta < best_delta) { 512 best_delta = delta; 513 best_div_val = div_val; 514 best_parent = i; 515 } 516 } 517 518 if (IS_ERR_VALUE(best_parent)) 519 return best_parent; 520 521 SET_PARM_VALUE(priv, mux->parm, best_parent); 522 /* Divider is set to (field value + 1), hence the decrement */ 523 SET_PARM_VALUE(priv, div->parm, best_div_val - 1); 524 525 return 0; 526} 527 528static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned int id, ulong rate); 529 530static ulong meson_mux_set_rate(struct clk *clk, unsigned long id, ulong rate) 531{ 532 int i; 533 ulong ret = -EINVAL; 534 struct meson_clk *priv = dev_get_priv(clk->dev); 535 const struct meson_clk_info *info; 536 537 info = meson_clk_get_info(clk, id, MESON_CLK_MUX); 538 if (IS_ERR(info)) 539 return PTR_ERR(info); 540 541 for (i = 0; i < (1 << info->parm->width); i++) { 542 ret = meson_clk_set_rate_by_id(clk, info->parents[i], rate); 543 if (!ret) { 544 SET_PARM_VALUE(priv, info->parm, i); 545 break; 546 } 547 } 548 549 return ret; 550} 551 552/* Rate propagation is implemented for a subcection of a clock tree, that is 553 * required at boot stage. 554 */ 555static ulong meson_clk_set_rate_by_id(struct clk *clk, unsigned int id, ulong rate) 556{ 557 switch (id) { 558 case CLKID_SPIFC_DIV: 559 case CLKID_USB_BUS_DIV: 560 return meson_composite_set_rate(clk, id, rate); 561 case CLKID_SPIFC: 562 case CLKID_USB_BUS: { 563 unsigned long parent = meson_clk_get_parent(clk, id); 564 565 return meson_clk_set_rate_by_id(clk, parent, rate); 566 } 567 case CLKID_SPIFC_SEL2: 568 return meson_mux_set_rate(clk, id, rate); 569 } 570 571 return -EINVAL; 572} 573 574static ulong meson_clk_set_rate(struct clk *clk, ulong rate) 575{ 576 return meson_clk_set_rate_by_id(clk, clk->id, rate); 577} 578 579static int meson_mux_set_parent_by_id(struct clk *clk, unsigned int parent_id) 580{ 581 unsigned int i, parent_index; 582 struct meson_clk *priv = dev_get_priv(clk->dev); 583 const struct meson_clk_info *info; 584 585 info = meson_clk_get_info(clk, clk->id, MESON_CLK_MUX); 586 if (IS_ERR(info)) 587 return PTR_ERR(info); 588 589 parent_index = -EINVAL; 590 for (i = 0; i < (1 << info->parm->width); i++) { 591 if (parent_id == info->parents[i]) { 592 parent_index = i; 593 break; 594 } 595 } 596 597 if (IS_ERR_VALUE(parent_index)) 598 return parent_index; 599 600 SET_PARM_VALUE(priv, info->parm, parent_index); 601 602 return 0; 603} 604 605static int meson_clk_set_parent(struct clk *clk, struct clk *parent_clk) 606{ 607 return meson_mux_set_parent_by_id(clk, parent_clk->id); 608} 609 610static int meson_clk_probe(struct udevice *dev) 611{ 612 struct meson_clk *priv = dev_get_priv(dev); 613 614 return regmap_init_mem(dev_ofnode(dev), &priv->map); 615} 616 617struct meson_clk_data meson_a1_peripherals_info = { 618 .clocks = meson_clocks, 619 .num_clocks = ARRAY_SIZE(meson_clocks), 620}; 621 622struct meson_clk_data meson_a1_pll_info = { 623 .clocks = meson_pll_clocks, 624 .num_clocks = ARRAY_SIZE(meson_pll_clocks), 625}; 626 627static const struct udevice_id meson_clk_ids[] = { 628 { 629 .compatible = "amlogic,a1-peripherals-clkc", 630 .data = (ulong)&meson_a1_peripherals_info, 631 }, 632 { 633 .compatible = "amlogic,a1-pll-clkc", 634 .data = (ulong)&meson_a1_pll_info, 635 }, 636 { } 637}; 638 639#if IS_ENABLED(CONFIG_CMD_CLK) 640static const char *meson_clk_get_name(struct clk *clk, int id) 641{ 642 const struct meson_clk_info *info; 643 644 info = meson_clk_get_info(clk, id, MESON_CLK_ANY); 645 646 return IS_ERR(info) ? "unknown" : info->name; 647} 648 649static int meson_clk_dump_single(struct clk *clk) 650{ 651 const struct meson_clk_info *info; 652 struct meson_clk *priv; 653 unsigned long rate; 654 char *state, frequency[80]; 655 int parent; 656 657 priv = dev_get_priv(clk->dev); 658 659 info = meson_clk_get_info(clk, clk->id, MESON_CLK_ANY); 660 if (IS_ERR(info) || !info->name) 661 return -EINVAL; 662 663 rate = clk_get_rate(clk); 664 if (IS_ERR_VALUE(rate)) 665 sprintf(frequency, "unknown"); 666 else 667 sprintf(frequency, "%lu", rate); 668 669 if (info->type == MESON_CLK_GATE) 670 state = GET_PARM_VALUE(priv, info->parm) ? "enabled" : "disabled"; 671 else 672 state = "N/A"; 673 674 parent = meson_clk_get_parent(clk, clk->id); 675 printf("%15s%20s%20s%15s\n", 676 info->name, 677 frequency, 678 meson_clk_get_name(clk, parent), 679 state); 680 681 return 0; 682} 683 684static void meson_clk_dump(struct udevice *dev) 685{ 686 int i; 687 struct meson_clk_data *data; 688 const char *sep = "--------------------"; 689 690 printf("%s:\n", dev->name); 691 printf("%.15s%s%s%.15s\n", sep, sep, sep, sep); 692 printf("%15s%20s%20s%15s\n", "clk", "frequency", "parent", "state"); 693 printf("%.15s%s%s%.15s\n", sep, sep, sep, sep); 694 695 data = (struct meson_clk_data *)dev_get_driver_data(dev); 696 for (i = 0; i < data->num_clocks; i++) { 697 meson_clk_dump_single(&(struct clk){ 698 .dev = dev, 699 .id = i 700 }); 701 } 702} 703#endif 704 705static struct clk_ops meson_clk_ops = { 706 .disable = meson_clk_disable, 707 .enable = meson_clk_enable, 708 .get_rate = meson_clk_get_rate, 709 .set_rate = meson_clk_set_rate, 710 .set_parent = meson_clk_set_parent, 711#if IS_ENABLED(CONFIG_CMD_CLK) 712 .dump = meson_clk_dump, 713#endif 714}; 715 716U_BOOT_DRIVER(meson_clk) = { 717 .name = "meson-clk-a1", 718 .id = UCLASS_CLK, 719 .of_match = meson_clk_ids, 720 .priv_auto = sizeof(struct meson_clk), 721 .ops = &meson_clk_ops, 722 .probe = meson_clk_probe, 723}; 724