clk/renesas/r9a06g032-clocks.c

617 	 * These are not hardware clocks, but are needed to handle the special
698 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
706 		parent_rate = clk_get_rate(&clocks->mclk);
717 static void clk_rdesc_set(struct r9a06g032_priv *clocks,
729 	regmap_update_bits(clocks->regmap, reg, mask, val);
732 static int clk_rdesc_get(struct r9a06g032_priv *clocks,
739 	regmap_read(clocks->regmap, reg, &val);
750 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
758 	clk_rdesc_set(clocks, g->reset, on);
768 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
777 	clk_rdesc_set(clocks, g->gate, on);
780 	clk_rdesc_set(clocks, g->reset, 1);
789 	clk_rdesc_set(clocks, g->ready, on);
792 	clk_rdesc_set(clocks, g->midle, !on);
832 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
837 	regmap_read(clocks->regmap, 4 * desc->reg, &div);
848 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
892 	regmap_write(clocks->regmap, 4 * desc->reg, div | BIT(31));
901 static int r9a06g032_clk_dualgate_setenable(struct r9a06g032_priv *clocks,
905 	u8 sel_bit = clk_rdesc_get(clocks, desc->dual.sel);
910 	clk_rdesc_set(clocks, gate[!sel_bit], 0);
911 	clk_rdesc_set(clocks, reset[!sel_bit], 1);
914 	clk_rdesc_set(clocks, gate[sel_bit], enable);
915 	clk_rdesc_set(clocks, reset[sel_bit], 1);
922 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
925 	return r9a06g032_clk_dualgate_setenable(clocks, desc, 1);
930 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
933 	return r9a06g032_clk_dualgate_setenable(clocks, desc, 0);
938 	struct r9a06g032_priv *clocks = dev_get_priv(clk->dev);
940 	u8 sel_bit = clk_rdesc_get(clocks, desc->dual.sel);
943 	return clk_rdesc_get(clocks, gate[sel_bit]);