Searched refs:clk (Results 1 - 25 of 956) sorted by relevance

1234567891011>>

/u-boot/arch/arm/mach-nexell/include/mach/
H A Dclk.h10 struct clk { struct
16 struct clk *clk_get(const char *id);
17 void clk_put(struct clk *clk);
18 unsigned long clk_get_rate(struct clk *clk);
19 long clk_round_rate(struct clk *clk, unsigned long rate);
20 int clk_set_rate(struct clk *clk, unsigne
[all...]
/u-boot/arch/arm/include/asm/kona-common/
H A Dclk.h13 struct clk;
17 struct clk *clk_get(const char *id);
18 int clk_enable(struct clk *clk);
19 void clk_disable(struct clk *clk);
20 unsigned long clk_get_rate(struct clk *clk);
21 long clk_round_rate(struct clk *clk, unsigne
[all...]
/u-boot/include/
H A Dclk-uclass.h11 /* See clk.h for background documentation. */
13 #include <clk.h>
32 int (*of_xlate)(struct clk *clock,
34 int (*request)(struct clk *clock);
35 ulong (*round_rate)(struct clk *clk, ulong rate);
36 ulong (*get_rate)(struct clk *clk);
37 ulong (*set_rate)(struct clk *clk, ulon
[all...]
H A Dclk.h28 * often has this capability. clk-uclass.h describes the interface which
38 * struct clk - A handle to (allowing control of) a single clock.
63 struct clk { struct
87 struct clk *clks;
98 * @clk: A pointer to a clock struct to initialise
120 struct clk *clk);
127 * @clk: A pointer to a clock struct to initialize.
137 int clk_get_by_index(struct udevice *dev, int index, struct clk *clk);
227 struct clk *clk = devm_clk_get(dev, id); local
252 clk_get_by_phandle(struct udevice *dev, const struct phandle_1_arg *cells, struct clk *clk) argument
259 clk_get_by_index(struct udevice *dev, int index, struct clk *clk) argument
265 clk_get_by_index_nodev(ofnode node, int index, struct clk *clk) argument
276 clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) argument
294 clk_get_by_name_nodev(ofnode node, const char *name, struct clk *clk) argument
299 clk_release_all(struct clk *clk, unsigned int count) argument
317 clk_get_by_name_optional(struct udevice *dev, const char *name, struct clk *clk) argument
341 clk_get_by_name_nodev_optional(ofnode node, const char *name, struct clk *clk) argument
566 clk_request(struct udevice *dev, struct clk *clk) argument
571 clk_get_rate(struct clk *clk) argument
576 clk_get_parent(struct clk *clk) argument
581 clk_get_parent_rate(struct clk *clk) argument
586 clk_round_rate(struct clk *clk, ulong rate) argument
591 clk_set_rate(struct clk *clk, ulong rate) argument
596 clk_set_parent(struct clk *clk, struct clk *parent) argument
601 clk_enable(struct clk *clk) argument
611 clk_disable(struct clk *clk) argument
631 clk_dev_binded(struct clk *clk) argument
643 clk_valid(struct clk *clk) argument
[all...]
/u-boot/drivers/clk/tegra/
H A Dtegra-car-clk.c7 #include <clk-uclass.h>
14 static int tegra_car_clk_request(struct clk *clk) argument
16 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
17 clk->id);
27 if (clk->id >= PERIPH_ID_COUNT)
33 static ulong tegra_car_clk_get_rate(struct clk *clk) argument
44 tegra_car_clk_set_rate(struct clk *clk, ulong rate) argument
55 tegra_car_clk_enable(struct clk *clk) argument
65 tegra_car_clk_disable(struct clk *clk) argument
[all...]
H A Dtegra186-clk.c7 #include <clk-uclass.h>
13 static ulong tegra186_clk_get_rate(struct clk *clk) argument
19 debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
20 clk->id);
22 req.cmd_and_id = (CMD_CLK_GET_RATE << 24) | clk->id;
24 ret = misc_call(clk->dev->parent, MRQ_CLK, &req, sizeof(req), &resp,
32 static ulong tegra186_clk_set_rate(struct clk *cl argument
52 tegra186_clk_en_dis(struct clk *clk, enum mrq_reset_commands cmd) argument
69 tegra186_clk_enable(struct clk *clk) argument
77 tegra186_clk_disable(struct clk *clk) argument
[all...]
/u-boot/drivers/clk/exynos/
H A DMakefile10 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk.o clk-pll.o
11 obj-$(CONFIG_CLK_EXYNOS7420) += clk-exynos7420.o
12 obj-$(CONFIG_CLK_EXYNOS850) += clk-exynos850.o
/u-boot/drivers/clk/mtmips/
H A DMakefile3 obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
4 obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
5 obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
/u-boot/drivers/clk/imx/
H A Dclk-imx8.h17 ulong imx8_clk_get_rate(struct clk *clk);
18 ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate);
19 int __imx8_clk_enable(struct clk *clk, bool enable);
H A DMakefile5 obj-$(CONFIG_$(SPL_TPL_)CLK_CCF) += clk-gate2.o clk-pllv3.o clk-pfd.o
6 obj-$(CONFIG_$(SPL_TPL_)CLK_IMX6Q) += clk-imx6q.o
7 obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
10 obj-$(CONFIG_IMX8QXP) += clk-imx8qxp.o
11 obj-$(CONFIG_IMX8QM) += clk-imx8qm.o
13 obj-$(CONFIG_$(SPL_TPL_)CLK_IMX8MM) += clk-imx8mm.o clk-pll14xx.o \
14 clk
[all...]
/u-boot/drivers/clk/mediatek/
H A DMakefile3 obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
6 obj-$(CONFIG_MT8512) += clk-mt8512.o
7 obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
8 obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
9 obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
10 obj-$(CONFIG_TARGET_MT7986) += clk-mt7986.o
11 obj-$(CONFIG_TARGET_MT7981) += clk-mt7981.o
12 obj-$(CONFIG_TARGET_MT7988) += clk-mt7988.o
13 obj-$(CONFIG_TARGET_MT8183) += clk-mt8183.o
14 obj-$(CONFIG_TARGET_MT8365) += clk
[all...]
/u-boot/arch/arm/mach-exynos/
H A Dclock_init_exynos4.c30 #include <asm/arch/clk.h>
41 struct exynos4_clock *clk = local
44 writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
48 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
49 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
50 writel(CLK_SRC_DMC_VAL, &clk->src_dmc);
51 writel(CLK_SRC_LEFTBUS_VAL, &clk->src_leftbus);
52 writel(CLK_SRC_RIGHTBUS_VAL, &clk->src_rightbus);
53 writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
54 writel(CLK_SRC_PERIL0_VAL, &clk
[all...]
/u-boot/drivers/clk/stm32/
H A DMakefile5 obj-$(CONFIG_CLK_STM32_CORE) += clk-stm32-core.o
6 obj-$(CONFIG_CLK_STM32F) += clk-stm32f.o
7 obj-$(CONFIG_CLK_STM32H7) += clk-stm32h7.o
8 obj-$(CONFIG_CLK_STM32MP1) += clk-stm32mp1.o
9 obj-$(CONFIG_CLK_STM32MP13) += clk-stm32mp13.o
/u-boot/drivers/clk/altera/
H A DMakefile6 obj-$(CONFIG_TARGET_SOCFPGA_AGILEX) += clk-agilex.o
7 obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += clk-arria10.o
8 obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-n5x.o
9 obj-$(CONFIG_TARGET_SOCFPGA_N5X) += clk-mem-n5x.o
10 obj-$(CONFIG_TARGET_SOCFPGA_AGILEX5) += clk-agilex5.o
/u-boot/drivers/clk/
H A Dclk.c10 #include <clk.h>
11 #include <clk-uclass.h>
18 int clk_register(struct clk *clk, const char *drv_name, argument
43 ret = device_bind(parent, drv, name, NULL, ofnode_null(), &clk->dev);
50 clk->enable_count = 0;
52 /* Store back pointer to clk from udevice */
54 dev_set_uclass_priv(clk->dev, clk);
59 ulong clk_generic_get_rate(struct clk *cl argument
72 clk_dev_binded(struct clk *clk) argument
82 ccf_clk_get_rate(struct clk *clk) argument
92 ccf_clk_set_rate(struct clk *clk, unsigned long rate) argument
102 ccf_clk_set_parent(struct clk *clk, struct clk *parent) argument
117 ccf_clk_endisable(struct clk *clk, bool enable) argument
127 ccf_clk_enable(struct clk *clk) argument
132 ccf_clk_disable(struct clk *clk) argument
[all...]
H A Dclk-gpio.c6 #include <clk.h>
7 #include <clk-uclass.h>
9 #include <linux/clk-provider.h>
15 struct clk *clk; /* Gated clock */ member in struct:clk_gpio_priv
18 static int clk_gpio_enable(struct clk *clk) argument
20 struct clk_gpio_priv *priv = dev_get_priv(clk->dev);
22 clk_enable(priv->clk);
28 static int clk_gpio_disable(struct clk *cl argument
38 clk_gpio_get_rate(struct clk *clk) argument
[all...]
H A Dclk_fixed_rate.c9 #include <clk-uclass.h>
13 #include <linux/clk-provider.h>
18 static ulong clk_fixed_rate_get_rate(struct clk *clk) argument
20 return to_clk_fixed_rate(clk->dev)->fixed_rate;
24 static int dummy_enable(struct clk *clk) argument
38 struct clk *clk = &plat->clk; local
51 clk_fixed_rate_raw_get_rate(struct clk *clk) argument
71 struct clk *clk; local
[all...]
H A Dclk-fixed-factor.c12 #include <clk.h>
13 #include <clk-uclass.h>
19 #include <linux/clk-provider.h>
22 #include "clk.h"
26 static ulong clk_factor_recalc_rate(struct clk *clk) argument
28 struct clk_fixed_factor *fix = to_clk_fixed_factor(clk);
29 unsigned long parent_rate = clk_get_parent_rate(clk);
41 struct clk *clk_hw_register_fixed_factor(struct device *dev,
46 struct clk *cl local
73 struct clk *clk; local
[all...]
/u-boot/drivers/clk/ti/
H A DMakefile6 obj-$(CONFIG_ARCH_OMAP2PLUS) += clk.o omap4-cm.o
8 obj-$(CONFIG_CLK_TI_AM3_DPLL) += clk-am3-dpll.o clk-am3-dpll-x2.o
9 obj-$(CONFIG_CLK_TI_CTRL) += clk-ctrl.o
10 obj-$(CONFIG_CLK_TI_DIVIDER) += clk-divider.o
11 obj-$(CONFIG_CLK_TI_GATE) += clk-gate.o
12 obj-$(CONFIG_CLK_TI_MUX) += clk-mux.o
13 obj-$(CONFIG_CLK_TI_SCI) += clk-sci.o
14 obj-$(CONFIG_$(SPL_TPL_)CLK_K3_PLL) += clk-k3-pll.o
15 obj-$(CONFIG_$(SPL_TPL_)CLK_K3) += clk
[all...]
/u-boot/arch/arm/cpu/armv7/bcm281xx/
H A DMakefile6 obj-y += clk-core.o
7 obj-y += clk-bcm281xx.o
8 obj-y += clk-sdio.o
9 obj-y += clk-bsc.o
10 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
11 obj-y += clk-usb-otg.o
/u-boot/arch/arm/cpu/armv7/bcm235xx/
H A DMakefile5 obj-y += clk-core.o
6 obj-y += clk-bcm235xx.o
7 obj-y += clk-sdio.o
8 obj-y += clk-bsc.o
9 obj-$(CONFIG_BCM_SF2_ETH) += clk-eth.o
10 obj-y += clk-usb-otg.o
/u-boot/drivers/adc/
H A Dstm32-adc-core.h29 #include <clk.h>
45 struct clk aclk;
46 struct clk bclk;
/u-boot/arch/arm/mach-imx/imx8/
H A Dclock.c13 u32 mxc_get_clock(enum mxc_clock clk) argument
15 switch (clk) {
17 printf("Unsupported mxc_clock %d\n", clk);
/u-boot/drivers/clk/uniphier/
H A DMakefile1 obj-y += clk-uniphier-core.o
2 obj-y += clk-uniphier-sys.o
3 obj-y += clk-uniphier-mio.o
/u-boot/drivers/clk/at91/
H A DMakefile2 # Makefile for at91 specific clk
6 obj-y += pmc.o sckc.o clk-main.o clk-master.o clk-programmable.o clk-system.o
7 obj-y += clk-peripheral.o
9 obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generic.o
10 obj-$(CONFIG_AT91_UTMI) += clk-utmi.o
11 obj-$(CONFIG_AT91_SAM9X60_PLL) += clk-sam9x60-pll.o
12 obj-$(CONFIG_AT91_SAM9X60_USB) += clk
[all...]

Completed in 128 milliseconds

1234567891011>>