Searched refs:cl (Results 1 - 25 of 27) sorted by relevance

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/u-boot/board/compulab/cl-som-imx7/
H A DMakefile16 obj-y += cl-som-imx7.o
/u-boot/board/compulab/imx8mm-cl-iot-gate/
H A DMakefile8 obj-y += imx8mm-cl-iot-gate.o
/u-boot/drivers/net/fsl-mc/dpio/
H A Dqbman_portal.c203 uint32_t *cl = qb_cl(d); local
205 qb_attr_code_encode(&code_eq_orp_en, cl, 0);
206 qb_attr_code_encode(&code_eq_cmd, cl,
215 uint32_t *cl = qb_cl(d); local
217 qb_attr_code_encode_64(&code_eq_rsp_lo, (uint64_t *)cl, storage_phys);
218 qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
225 uint32_t *cl = qb_cl(d); local
227 qb_attr_code_encode(&code_eq_qd_en, cl, 1);
228 qb_attr_code_encode(&code_eq_tgt_id, cl, qdid);
229 qb_attr_code_encode(&code_eq_qd_bin, cl, qd_bi
241 const uint32_t *cl = qb_cl(d); local
289 uint32_t *cl = qb_cl(d); local
305 uint32_t *cl = qb_cl(d); local
314 uint32_t *cl = qb_cl(d); local
321 uint32_t *cl = qb_cl(d); local
331 uint32_t *cl = qb_cl(d); local
528 uint32_t *cl; local
537 uint32_t *cl = qb_cl(d); local
550 const uint32_t *cl = qb_cl(d); local
[all...]
/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_spd.c593 u32 cs, cl, cs_num, cs_ena; local
712 cl = ddr3_get_max_val(ddr3_div(sum_info.min_cas_lat_time,
716 cl = ddr3_div(sum_info.min_cas_lat_time, ddr_clk_time, 0);
718 if (cl < 5)
719 cl = 5;
721 DEBUG_INIT_FULL_C("DDR3 - DUNIT-SET - Cas Latency = ", cl, 1);
782 if (cl != 3)
858 if (cl < 7)
1050 reg |= (cl << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs));
1061 reg |= ((cl
[all...]
H A Dddr3_init.h107 u32 ddr3_cl_to_valid_cl(u32 cl);
H A Dddr3_hw_training.h267 u32 cl; member in struct:dram_info
323 u32 ddr3_cl_to_valid_cl(u32 cl);
H A Dddr3_dfs.c988 tmp = ddr3_cl_to_valid_cl(dram_info->cl);
1172 tmp = ddr3_cl_to_valid_cl(dram_info->cl);
1479 tmp = ddr3_cl_to_valid_cl(dram_info->cl) & 0xF;
1511 reg |= (dram_info->cl <<
1519 reg |= ((dram_info->cl + 1) <<
H A Dddr3_read_leveling.c223 reg |= (dram_info->cl <<
233 reg |= ((dram_info->cl + 1) <<
237 reg |= ((dram_info->cl + 2) <<
415 rd_sample_delay = dram_info->cl;
767 rd_sample_delay = dram_info->cl;
H A Dddr3_init.c960 u32 ddr3_cl_to_valid_cl(u32 cl) argument
962 switch (cl) {
H A Dddr3_hw_training.c137 dram_info.cl = ddr3_valid_cl_to_cl(reg);
/u-boot/arch/x86/cpu/quark/
H A Ddram.c108 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0);
121 mrc_params->params.density, mrc_params->params.cl,
H A Dsmc.c83 tcl = mrc_params->params.cl; /* CAS latency in clocks */
266 cas = mrc_params->params.cl;
/u-boot/arch/x86/include/asm/arch-quark/
H A Dmrc.h50 * cl: DRAM CAS Latency in clocks
62 uint8_t cl; member in struct:dram_params
/u-boot/lib/
H A Dstring.c530 unsigned long cl = 0; local
536 cl <<= 8;
537 cl |= c & 0xff;
540 *sl++ = cl;
/u-boot/drivers/bios_emulator/include/
H A Dbiosemu.h203 cl - Value of the CL register
215 u8 ch, cl; member in struct:__anon644
227 u8 cl; member in struct:__anon645
/u-boot/drivers/ddr/marvell/a38x/
H A Dmv_ddr_topology.c18 unsigned int cl = ceil_div(taa_min, tclk); local
20 return mv_ddr_spd_supported_cl_get(cl);
117 /* update cas latency (cl) */
H A Dmv_ddr_spd.h291 unsigned int mv_ddr_spd_supported_cl_get(unsigned int cl);
H A Dmv_ddr4_mpr_pda_if.c43 u32 cl, cwl; local
63 cl = tm->interface_params[if_id].cas_l;
82 val = ((cl_mask_table[cl] & 0x1) << 2) |
83 (((cl_mask_table[cl] & 0xe) >> 1) << 4) |
H A Dmv_ddr_spd.c41 unsigned int mv_ddr_spd_supported_cl_get(unsigned int cl) argument
47 mv_ddr_spd_supported_cls[i] < cl)
/u-boot/arch/arm/dts/
H A DMakefile1278 dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE) += imx8mm-cl-iot-gate.dtb \
1279 imx8mm-cl-iot-gate-ied.dtbo \
1280 imx8mm-cl-iot-gate-ied-adc0.dtbo \
1281 imx8mm-cl-iot-gate-ied-adc1.dtbo \
1282 imx8mm-cl-iot-gate-ied-can0.dtbo \
1283 imx8mm-cl-iot-gate-ied-can1.dtbo \
1284 imx8mm-cl-iot-gate-ied-tpm0.dtbo \
1285 imx8mm-cl-iot-gate-ied-tpm1.dtbo
1287 dtb-$(CONFIG_TARGET_IMX8MM_CL_IOT_GATE_OPTEE) += imx8mm-cl-iot-gate-optee.dtb \
1288 imx8mm-cl
[all...]
/u-boot/drivers/ram/octeon/
H A Docteon3_lmc.c2610 static int cl __section(".data");
3200 cl = simple_strtoul(s, NULL, 0);
3202 cl);
3206 mp0.s.cl = 0x0;
3207 if (cl > 9)
3208 mp0.s.cl = 0x1;
3209 if (cl > 10)
3210 mp0.s.cl = 0x2;
3211 if (cl > 11)
3212 mp0.s.cl
[all...]
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-sso-defs.h2797 u64 cl : 5; member in struct:cvmx_sso_xaqx_head_ptr::cvmx_sso_xaqx_head_ptr_s
2844 u64 cl : 5; member in struct:cvmx_sso_xaqx_tail_ptr::cvmx_sso_xaqx_tail_ptr_s
H A Dcvmx-pki-defs.h1350 u64 cl : 2; member in struct:cvmx_pki_pcam_lookup::cvmx_pki_pcam_lookup_s
H A Dcvmx-lmcx-defs.h2332 uint64_t cl:4; member in struct:cvmx_lmcx_modereg_params0::cvmx_lmcx_modereg_params0_s
2350 uint64_t cl:4; member in struct:cvmx_lmcx_modereg_params0::cvmx_lmcx_modereg_params0_cn61xx
/u-boot/drivers/ram/rockchip/
H A Dsdram_rv1126.c1789 u32 mr_tmp, cl, cwl, phy_fsp, offset = 0; local
1794 cl = readl(PHY_REG(phy_base, offset));
1882 clrsetbits_le32(PHY_REG(phy_base, offset), 0x1f, cl); local
2845 /* cl cwl al update */

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