1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6#include <common.h> 7#include <cpu_func.h> 8#include <errno.h> 9#include <fdtdec.h> 10#include <init.h> 11#include <log.h> 12#include <malloc.h> 13#include <asm/cache.h> 14#include <asm/global_data.h> 15#include <asm/mrccache.h> 16#include <asm/mtrr.h> 17#include <asm/post.h> 18#include <asm/arch/mrc.h> 19#include <asm/arch/msg_port.h> 20#include <asm/arch/quark.h> 21 22DECLARE_GLOBAL_DATA_PTR; 23 24static __maybe_unused int prepare_mrc_cache(struct mrc_params *mrc_params) 25{ 26 struct mrc_data_container *cache; 27 struct mrc_region entry; 28 int ret; 29 30 ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry); 31 if (ret) 32 return ret; 33 34 cache = mrccache_find_current(&entry); 35 if (!cache) 36 return -ENOENT; 37 38 debug("%s: mrc cache at %p, size %x checksum %04x\n", __func__, 39 cache->data, cache->data_size, cache->checksum); 40 41 /* copy mrc cache to the mrc_params */ 42 memcpy(&mrc_params->timings, cache->data, cache->data_size); 43 44 return 0; 45} 46 47static int mrc_configure_params(struct mrc_params *mrc_params) 48{ 49 const void *blob = gd->fdt_blob; 50 int node; 51 int mrc_flags; 52 53 node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_QRK_MRC); 54 if (node < 0) { 55 debug("%s: Cannot find MRC node\n", __func__); 56 return -EINVAL; 57 } 58 59#ifdef CONFIG_ENABLE_MRC_CACHE 60 mrc_params->boot_mode = prepare_mrc_cache(mrc_params); 61 if (mrc_params->boot_mode) 62 mrc_params->boot_mode = BM_COLD; 63 else 64 mrc_params->boot_mode = BM_FAST; 65#else 66 mrc_params->boot_mode = BM_COLD; 67#endif 68 69 /* 70 * TODO: 71 * 72 * We need determine ECC by pin strap state 73 * 74 * Disable ECC by default for now 75 */ 76 mrc_params->ecc_enables = 0; 77 78 mrc_flags = fdtdec_get_int(blob, node, "flags", 0); 79 if (mrc_flags & MRC_FLAG_SCRAMBLE_EN) 80 mrc_params->scrambling_enables = 1; 81 else 82 mrc_params->scrambling_enables = 0; 83 84 mrc_params->dram_width = fdtdec_get_int(blob, node, "dram-width", 0); 85 mrc_params->ddr_speed = fdtdec_get_int(blob, node, "dram-speed", 0); 86 mrc_params->ddr_type = fdtdec_get_int(blob, node, "dram-type", 0); 87 88 mrc_params->rank_enables = fdtdec_get_int(blob, node, "rank-mask", 0); 89 mrc_params->channel_enables = fdtdec_get_int(blob, node, 90 "chan-mask", 0); 91 mrc_params->channel_width = fdtdec_get_int(blob, node, 92 "chan-width", 0); 93 mrc_params->address_mode = fdtdec_get_int(blob, node, "addr-mode", 0); 94 95 mrc_params->refresh_rate = fdtdec_get_int(blob, node, 96 "refresh-rate", 0); 97 mrc_params->sr_temp_range = fdtdec_get_int(blob, node, 98 "sr-temp-range", 0); 99 mrc_params->ron_value = fdtdec_get_int(blob, node, 100 "ron-value", 0); 101 mrc_params->rtt_nom_value = fdtdec_get_int(blob, node, 102 "rtt-nom-value", 0); 103 mrc_params->rd_odt_value = fdtdec_get_int(blob, node, 104 "rd-odt-value", 0); 105 106 mrc_params->params.density = fdtdec_get_int(blob, node, 107 "dram-density", 0); 108 mrc_params->params.cl = fdtdec_get_int(blob, node, "dram-cl", 0); 109 mrc_params->params.ras = fdtdec_get_int(blob, node, "dram-ras", 0); 110 mrc_params->params.wtr = fdtdec_get_int(blob, node, "dram-wtr", 0); 111 mrc_params->params.rrd = fdtdec_get_int(blob, node, "dram-rrd", 0); 112 mrc_params->params.faw = fdtdec_get_int(blob, node, "dram-faw", 0); 113 114 debug("MRC dram_width %d\n", mrc_params->dram_width); 115 debug("MRC rank_enables %d\n", mrc_params->rank_enables); 116 debug("MRC ddr_speed %d\n", mrc_params->ddr_speed); 117 debug("MRC flags: %s\n", 118 (mrc_params->scrambling_enables) ? "SCRAMBLE_EN" : ""); 119 120 debug("MRC density=%d tCL=%d tRAS=%d tWTR=%d tRRD=%d tFAW=%d\n", 121 mrc_params->params.density, mrc_params->params.cl, 122 mrc_params->params.ras, mrc_params->params.wtr, 123 mrc_params->params.rrd, mrc_params->params.faw); 124 125 return 0; 126} 127 128int dram_init(void) 129{ 130 struct mrc_params mrc_params; 131#ifdef CONFIG_ENABLE_MRC_CACHE 132 char *cache; 133#endif 134 int ret; 135 136 memset(&mrc_params, 0, sizeof(struct mrc_params)); 137 ret = mrc_configure_params(&mrc_params); 138 if (ret) 139 return ret; 140 141 /* Set up the DRAM by calling the memory reference code */ 142 mrc_init(&mrc_params); 143 if (mrc_params.status) 144 return -EIO; 145 146 gd->ram_size = mrc_params.mem_size; 147 post_code(POST_DRAM); 148 149 /* variable range MTRR#2: RAM area */ 150 disable_caches(); 151 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYBASE(MTRR_VAR_RAM), 152 0 | MTRR_TYPE_WRBACK); 153 msg_port_write(MSG_PORT_HOST_BRIDGE, MTRR_VAR_PHYMASK(MTRR_VAR_RAM), 154 (~(gd->ram_size - 1)) | MTRR_PHYS_MASK_VALID); 155 enable_caches(); 156 157#ifdef CONFIG_ENABLE_MRC_CACHE 158 cache = malloc(sizeof(struct mrc_timings)); 159 if (cache) { 160 struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL]; 161 162 memcpy(cache, &mrc_params.timings, sizeof(struct mrc_timings)); 163 mrc->buf = cache; 164 mrc->len = sizeof(struct mrc_timings); 165 } 166#endif 167 168 return 0; 169} 170 171int dram_init_banksize(void) 172{ 173 gd->bd->bi_dram[0].start = 0; 174 gd->bd->bi_dram[0].size = gd->ram_size; 175 176 return 0; 177} 178 179/* 180 * This function looks for the highest region of memory lower than 4GB which 181 * has enough space for U-Boot where U-Boot is aligned on a page boundary. 182 * It overrides the default implementation found elsewhere which simply 183 * picks the end of ram, wherever that may be. The location of the stack, 184 * the relocation address, and how far U-Boot is moved by relocation are 185 * set in the global data structure. 186 */ 187phys_addr_t board_get_usable_ram_top(phys_size_t total_size) 188{ 189 return gd->ram_size; 190} 191