/u-boot/arch/arm/cpu/armv7/s5p-common/ |
H A D | sromc.c | 25 tmp = srom->bw; 28 srom->bw = tmp;
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/u-boot/drivers/ram/rockchip/ |
H A D | sdram_common.c | 53 printdec(8 << cap_info->bw); 155 cap[0] = 1llu << (cap_info->bw + cap_info->col + 159 cap[1] = 1llu << (cap_info->bw + cap_info->col + 196 *p_os_reg2 |= SYS_REG_ENC_BW(cap_info->bw, channel); 222 u32 bw = cap_info->bw; local 227 (1ul << (col + bw - 1ul))); 248 u32 bw = cap_info->bw; local 251 (1ul << (coltmp + bktmp + bw 271 u32 bw = cap_info->bw; local 291 u32 row, col, bk, bw, cs_cap, cs; local 338 u32 bw = cap_info->bw; local 364 u32 bw = cap_info->bw; local 395 u32 row = 0, bktmp, coltmp, bw; local [all...] |
H A D | sdram_px30.c | 212 u32 bw, die_bw, col, bank; local 216 bw = cap_info->bw; 223 ddrconf = 7 + bw; 225 ddrconf = 12 - bw; 228 tmp = ((bank - 2) << 3) | (col + bw - 10); 263 cs_pst = cap_info->bw + cap_info->col + 297 if (sdram_params->base.dramtype == DDR4 && cap_info->bw != 0x2) 323 u32 i, bw; local 325 bw 374 dram_set_bw(struct dram_info *dram, u32 bw) argument 581 u32 bw = 1; local [all...] |
H A D | sdram_phy_px30.c | 97 void phy_dram_set_bw(void __iomem *phy_base, u32 bw) argument 99 if (bw == 2) { 103 } else if (bw == 1) { 107 } else if (bw == 0) { 173 struct sdram_base_params *base, u32 bw) 182 if (bw == 2) { 184 } else if (bw == 1) { 171 phy_cfg(void __iomem *phy_base, struct ddr_phy_regs *phy_regs, struct ddr_phy_skew *skew, struct sdram_base_params *base, u32 bw) argument
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H A D | sdram_rk322x.c | 236 u32 bw = (readl(&ddr_phy->ddrphy_reg[0]) >> 4) & 0xf; local 265 ret = (ret & 0xf) ^ bw; 378 /* bw: 2: 32bit, 1:16bit */ 379 static void set_bw(struct dram_info *dram, u32 bw) argument 385 if (bw == 1) { 406 u32 bw; local 409 if (sdram_params->ch[0].bw == 2) 410 bw = GRF_DDR_32BIT_EN | GRF_MSCH_NOC_32BIT_EN; 412 bw = GRF_MSCH_NOC_16BIT_EN; 437 writel(bw | GRF_DDR3_E 604 u32 bw, row, col, addr; local [all...] |
H A D | sdram_rk3328.c | 139 u32 cs, bw, die_bw, col, row, bank; local 145 bw = cap_info->bw; 156 tmp = ((row - 13) << 3) | (1 << 2) | (bw & 0x2) | 169 tmp = ((cs - 1) << 6) | ((row - 13) << 3) | (bw & 0x2) | die_bw; 188 if ((bw + col - 11) == (ddr_cfg_2_rbc[i] & 196 tmp = ((row - 13) << 4) | (1 << 2) | ((bw + col - 11) << 0); 227 if (sdram_params->base.dramtype == DDR4 && cap_info->bw == 0x1) 368 &sdram_params->base, cap_info->bw); 408 * default bw 414 u32 bw = 1; local [all...] |
H A D | sdram-px30-ddr3-detect-333.inc | 7 .bw = 0x1,
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H A D | sdram-px30-ddr4-detect-333.inc | 7 .bw = 0x1,
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H A D | sdram-px30-lpddr2-detect-333.inc | 7 .bw = 0x1,
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H A D | sdram-px30-lpddr3-detect-333.inc | 7 .bw = 0x1,
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H A D | sdram-rv1126-ddr3-detect-1056.inc | 7 .bw = 0x0,
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H A D | sdram-rv1126-ddr3-detect-328.inc | 7 .bw = 0x0,
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H A D | sdram-rv1126-ddr3-detect-396.inc | 7 .bw = 0x0,
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H A D | sdram-rv1126-ddr3-detect-528.inc | 7 .bw = 0x0,
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H A D | sdram-rv1126-ddr3-detect-664.inc | 7 .bw = 0x0,
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H A D | sdram-rv1126-ddr3-detect-784.inc | 7 .bw = 0x0,
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/u-boot/arch/mips/mach-mtmips/ |
H A D | ddr_init.c | 69 u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw) 88 if (bw) { 90 val |= (bw << IND_SDRAM_WIDTH_S) & IND_SDRAM_WIDTH_M; 104 u32 bw = 0; local 113 bw = IND_SDRAM_WIDTH_16BIT; 115 bw = IND_SDRAM_WIDTH_8BIT; 119 param->dqs_dly, param->mc_reset, bw); 139 param->dqs_dly, param->mc_reset, bw); 143 param->bus_width = bw; 149 u32 bw local 68 mc_ddr_init(void __iomem *memc, const struct mc_ddr_cfg *cfg, u32 dq_dly, u32 dqs_dly, mc_reset_t mc_reset, u32 bw) argument [all...] |
/u-boot/board/rockchip/evb_rk3036/ |
H A D | evb_rk3036.c | 24 /* 16bit bw */ 25 config->bw = 1;
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/u-boot/arch/arm/mach-exynos/include/mach/ |
H A D | sromc.h | 28 unsigned int bw; member in struct:s5p_sromc
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/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
H A D | sromc.h | 31 unsigned int bw; member in struct:s5p_sromc
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/u-boot/board/rockchip/kylin_rk3036/ |
H A D | kylin_rk3036.c | 27 /* 16bit bw */ 28 config->bw = 1;
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/u-boot/arch/arm/include/asm/arch-rockchip/ |
H A D | sdram_phy_px30.h | 60 void phy_dram_set_bw(void __iomem *phy_base, u32 bw); 63 struct sdram_base_params *base, u32 bw);
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H A D | sdram_rk3288.h | 20 u8 bw; member in struct:rk3288_sdram_channel
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/u-boot/arch/mips/mach-mtmips/include/mach/ |
H A D | ddr.h | 54 void ddr_calibrate(void __iomem *memc, u32 memsize, u32 bw);
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/u-boot/drivers/video/nexell/soc/ |
H A D | s5pxx18_soc_mlc.c | 501 u32 bw[3] = { local 513 bw[0] = 5; 514 bw[1] = 6; 515 bw[2] = 5; 521 bw[0] = 5; 522 bw[1] = 6; 523 bw[2] = 5; 530 bw[0] = 5; 531 bw[1] = 5; 532 bw[ [all...] |