Searched refs:bit (Results 1 - 25 of 216) sorted by relevance

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/u-boot/arch/sandbox/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/arch/x86/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/arch/xtensa/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/arch/microblaze/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/arch/mips/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/arch/nios2/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/arch/arm/dts/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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H A Dstm32h7-rcc.h18 #define STM32H7_AHB3_RESET(bit) (STM32H7_RCC_AHB3_##bit + (0x7C * 8))
30 #define STM32H7_AHB1_RESET(bit) (STM32H7_RCC_AHB1_##bit + (0x80 * 8))
39 #define STM32H7_AHB2_RESET(bit) (STM32H7_RCC_AHB2_##bit + (0x84 * 8))
58 #define STM32H7_AHB4_RESET(bit) (STM32H7_RCC_AHB4_##bit + (0x88 * 8))
64 #define STM32H7_APB3_RESET(bit) (STM32H7_RCC_APB3_##bit
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/u-boot/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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/u-boot/dts/upstream/include/dt-bindings/mfd/
H A Dstm32f4-rcc.h34 #define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit)
44 #define STM32F4_AHB2_RESET(bit) (STM32F4_RCC_AHB2_##bit + (0x14 * 8))
45 #define STM32F4_AHB2_CLOCK(bit) (STM32F4_RCC_AHB2_##bit + 0x20)
51 #define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit
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H A Dstm32f7-rcc.h34 #define STM32F7_AHB1_RESET(bit) (STM32F7_RCC_AHB1_##bit + (0x10 * 8))
35 #define STM32F7_AHB1_CLOCK(bit) (STM32F7_RCC_AHB1_##bit)
45 #define STM32F7_AHB2_RESET(bit) (STM32F7_RCC_AHB2_##bit + (0x14 * 8))
46 #define STM32F7_AHB2_CLOCK(bit) (STM32F7_RCC_AHB2_##bit + 0x20)
52 #define STM32F7_AHB3_RESET(bit) (STM32F7_RCC_AHB3_##bit
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