Searched refs:SRDS_PLLCR0_FRATE_SEL_5_15 (Results 1 - 3 of 3) sorted by relevance

/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h317 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 macro
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h553 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 macro
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2204 #define SRDS_PLLCR0_FRATE_SEL_5_15 0x00060000 macro

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