Searched refs:SRDS_PLLCR0_FRATE_SEL_5 (Results 1 - 3 of 3) sorted by relevance

/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h315 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h551 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2201 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro
2282 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 macro

Completed in 139 milliseconds