Searched refs:SRDS_PLLCR0_FRATE_SEL_3_75 (Results 1 - 4 of 4) sorted by relevance

/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dfsl_corenet2_serdes.c254 case SRDS_PLLCR0_FRATE_SEL_3_75:
/u-boot/arch/arm/include/asm/arch-ls102xa/
H A Dimmap_ls102xa.h316 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 macro
/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dimmap_lsch2.h552 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 macro
/u-boot/arch/powerpc/include/asm/
H A Dimmap_85xx.h2203 #define SRDS_PLLCR0_FRATE_SEL_3_75 0x00050000 macro

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