Searched refs:RCB_REG (Results 1 - 13 of 13) sorted by relevance
/u-boot/arch/x86/cpu/ivybridge/ |
H A D | lpc.c | 231 setbits_le32(RCB_REG(0x3310), (1 << 4) | (1 << 5) | (1 << 0)); 232 clrbits_le32(RCB_REG(0x3f02), 0xf); 260 setbits_le32(RCB_REG(0x2238), (1 << 6) | (1 << 0)); 262 setbits_le32(RCB_REG(0x228c), 1 << 0); 263 setbits_le32(RCB_REG(0x1100), (1 << 13) | (1 << 14)); 264 setbits_le32(RCB_REG(0x0900), 1 << 14); 265 writel(0xc0388400, RCB_REG(0x2304)); 266 setbits_le32(RCB_REG(0x2314), (1 << 5) | (1 << 18)); 267 setbits_le32(RCB_REG(0x2320), (1 << 15) | (1 << 1)); 268 clrsetbits_le32(RCB_REG( [all...] |
H A D | bd82x6x.c | 107 data = readl(RCB_REG(IOBPS)); 123 writel(address, RCB_REG(IOBPIRI)); 127 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); 129 writel(IOBPS_READ_AX, RCB_REG(IOBPS)); 134 data = readl(RCB_REG(IOBPD)); 139 if ((readl(RCB_REG(IOBPS)) & 0x6) != 0) { 150 writel(IOBPS_RW_BX, RCB_REG(IOBPS)); 152 writel(IOBPS_WRITE_AX, RCB_REG(IOBPS)); 157 writel(data, RCB_REG(IOBPD));
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H A D | sdram.c | 379 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP)); 380 writel(NOINT << D30IP_PIP, RCB_REG(D30IP)); 381 writel(INTA << D29IP_E1P, RCB_REG(D29IP)); 382 writel(INTA << D28IP_P3IP, RCB_REG(D28IP)); 383 writel(INTA << D27IP_ZIP, RCB_REG(D27IP)); 384 writel(INTA << D26IP_E2P, RCB_REG(D26IP)); 385 writel(NOINT << D25IP_LIP, RCB_REG(D25IP)); 386 writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP)); 389 writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR)); 390 writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29I [all...] |
/u-boot/arch/x86/cpu/broadwell/ |
H A D | iobp.c | 36 u16 status = readw(RCB_REG(IOBPS)); 52 writel(address, RCB_REG(IOBPIRI)); 55 clrsetbits_le16(RCB_REG(IOBPS), IOBPS_MASK, op); 65 writew(IOBPU_MAGIC, RCB_REG(IOBPU)); 68 setbits_le16(RCB_REG(IOBPS), IOBPS_READY); 74 status = readw(RCB_REG(IOBPS)); 91 return readl(RCB_REG(IOBPD)); 99 writel(data, RCB_REG(IOBPD)); 129 writel(addr, RCB_REG(IOBPIRI)); 130 clrsetbits_le16(RCB_REG(IOBP [all...] |
H A D | pch.c | 54 writew(0x1000, RCB_REG(OIC)); 56 readw(RCB_REG(OIC)); 59 clrsetbits_le32(RCB_REG(HPTC), 3, 1 << 7); 61 readl(RCB_REG(HPTC)); 65 setbits_le32(RCB_REG(GCS), 1 << 5); 103 setbits_le32(RCB_REG(0x3310), 0x0000002f); 104 clrsetbits_le32(RCB_REG(0x3f02), 0x0000000f, 0); 106 setbits_le32(RCB_REG(0x2314), 1 << 31 | 1 << 7); 107 setbits_le32(RCB_REG(0x1114), 1 << 15 | 1 << 14); 214 clrbits_le32(RCB_REG( [all...] |
H A D | adsp.c | 89 setbits_le32(RCB_REG(0x3350), 1 << 10); 102 setbits_le32(RCB_REG(ACPIIRQEN), ADSP_ACPI_IRQEN);
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H A D | sata.c | 113 reg32 = readl(RCB_REG(0x3a84)); 120 writel(reg32, RCB_REG(0x3a84)); 196 clrsetbits_le32(RCB_REG(0x333c), 0x00300000, 0x00c00000);
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H A D | cpu_full.c | 285 pmsync = readl(RCB_REG(PMSYNC_CONFIG)); 286 pmsync2 = readl(RCB_REG(PMSYNC_CONFIG2)); 301 writel(pmsync, RCB_REG(PMSYNC_CONFIG)); 320 writel(pmsync2, RCB_REG(PMSYNC_CONFIG2));
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/u-boot/arch/x86/include/asm/ |
H A D | intel_regs.h | 22 #define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg)) macro
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/u-boot/arch/x86/include/asm/arch-broadwell/ |
H A D | spi.h | 17 #define SPI_REG(x) (RCB_REG(SPIBAR_OFFSET + (x)))
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/u-boot/arch/x86/cpu/intel_common/ |
H A D | lpc.c | 35 clrbits_le32(RCB_REG(GCS), 4);
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H A D | cpu.c | 59 writel(1 << 2, RCB_REG(RC)); 104 clrsetbits_le32(RCB_REG(SOFT_RESET_DATA), 0x3f << 6, 110 setbits_le32(RCB_REG(SOFT_RESET_CTRL), 1);
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/u-boot/drivers/video/ |
H A D | ivybridge_igd.c | 732 writew(0x0010, RCB_REG(DISPBDF)); 733 setbits_le32(RCB_REG(FD2), PCH_ENABLE_DBDF);
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