1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2014 Google Inc.
4 *
5 * This file is from coreboot soc/intel/broadwell/include/soc/spi.h
6 */
7
8#ifndef _BROADWELL_SPI_H_
9#define _BROADWELL_SPI_H_
10
11/*
12 * SPI Opcode Menu setup for SPIBAR lockdown
13 * should support most common flash chips.
14 */
15
16#define SPIBAR_OFFSET		0x3800
17#define SPI_REG(x)		(RCB_REG(SPIBAR_OFFSET + (x)))
18
19/* Reigsters within the SPIBAR */
20#define SPIBAR_SSFC		0x91
21#define SPIBAR_FDOC		0xb0
22#define SPIBAR_FDOD		0xb4
23
24#define SPIBAR_PREOP		0x94
25#define SPIBAR_OPTYPE		0x96
26#define SPIBAR_OPMENU_LOWER	0x98
27#define SPIBAR_OPMENU_UPPER	0x9c
28
29#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
30#define SPI_OPTYPE_0 0x01 /* Write, no address */
31
32#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
33#define SPI_OPTYPE_1 0x03 /* Write, address required */
34
35#define SPI_OPMENU_2 0x03 /* READ: Read Data */
36#define SPI_OPTYPE_2 0x02 /* Read, address required */
37
38#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
39#define SPI_OPTYPE_3 0x00 /* Read, no address */
40
41#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
42#define SPI_OPTYPE_4 0x03 /* Write, address required */
43
44#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
45#define SPI_OPTYPE_5 0x00 /* Read, no address */
46
47#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
48#define SPI_OPTYPE_6 0x03 /* Write, address required */
49
50#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
51#define SPI_OPTYPE_7 0x02 /* Read, address required */
52
53#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
54			  (SPI_OPMENU_5 << 8) | SPI_OPMENU_4)
55#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
56			  (SPI_OPMENU_1 << 8) | SPI_OPMENU_0)
57
58#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
59		    (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) |  \
60		    (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) |	  \
61		    (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0))
62
63#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
64
65#define SPIBAR_HSFS                 0x04   /* SPI hardware sequence status */
66#define  SPIBAR_HSFS_FLOCKDN        (1 << 15)/* Flash Configuration Lock-Down */
67#define  SPIBAR_HSFS_SCIP           (1 << 5) /* SPI Cycle In Progress */
68#define  SPIBAR_HSFS_AEL            (1 << 2) /* SPI Access Error Log */
69#define  SPIBAR_HSFS_FCERR          (1 << 1) /* SPI Flash Cycle Error */
70#define  SPIBAR_HSFS_FDONE          (1 << 0) /* SPI Flash Cycle Done */
71#define SPIBAR_HSFC                 0x06   /* SPI hardware sequence control */
72#define  SPIBAR_HSFC_BYTE_COUNT(c)  (((c - 1) & 0x3f) << 8)
73#define  SPIBAR_HSFC_CYCLE_READ     (0 << 1) /* Read cycle */
74#define  SPIBAR_HSFC_CYCLE_WRITE    (2 << 1) /* Write cycle */
75#define  SPIBAR_HSFC_CYCLE_ERASE    (3 << 1) /* Erase cycle */
76#define  SPIBAR_HSFC_GO             (1 << 0) /* GO: start SPI transaction */
77#define SPIBAR_FADDR                0x08   /* SPI flash address */
78#define SPIBAR_FDATA(n)             (0x10 + (4 * n)) /* SPI flash data */
79#define SPIBAR_SSFS                 0x90
80#define  SPIBAR_SSFS_ERROR          (1 << 3)
81#define  SPIBAR_SSFS_DONE           (1 << 2)
82#define SPIBAR_SSFC                 0x91
83#define  SPIBAR_SSFC_DATA           (1 << 14)
84#define  SPIBAR_SSFC_GO             (1 << 1)
85
86#endif
87