Searched refs:M5 (Results 1 - 6 of 6) sorted by relevance
| /u-boot/arch/x86/include/asm/arch-braswell/ |
| H A D | gpio.h | 19 M5, enumerator in enum:mode_list
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| /u-boot/board/ti/dra7xx/ |
| H A D | mux_data.h | 189 {XREF_CLK1, (M5 | PIN_OUTPUT)}, /* xref_clk1.atl_clk1 */
190 {XREF_CLK2, (M5 | PIN_OUTPUT)}, /* xref_clk2.atl_clk2 */
219 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
303 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
669 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
857 {XREF_CLK2, (M5 | PIN_INPUT_PULLDOWN)}, /* xref_clk2.atl_clk2 */
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| /u-boot/arch/arm/include/asm/arch-omap4/ |
| H A D | mux_omap4.h | 52 #define M5 5 macro
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| /u-boot/arch/arm/include/asm/arch-omap3/ |
| H A D | mux.h | 46 #define M5 5 macro
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| /u-boot/arch/arm/include/asm/arch-omap5/ |
| H A D | mux_dra7xx.h | 34 #define M5 5 macro
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| /u-boot/board/intel/cherryhill/ |
| H A D | cherryhill.c | 64 GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
67 GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
70 GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
73 GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
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Completed in 163 milliseconds