1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * (C) Copyright 2004-2009 4 * Texas Instruments Incorporated 5 * Richard Woodruff <r-woodruff2@ti.com> 6 * Aneesh V <aneesh@ti.com> 7 * Balaji Krishnamoorthy <balajitk@ti.com> 8 */ 9#ifndef _MUX_OMAP4_H_ 10#define _MUX_OMAP4_H_ 11 12#include <asm/types.h> 13 14struct pad_conf_entry { 15 16 u16 offset; 17 18 u16 val; 19 20}; 21 22#ifdef CONFIG_OFF_PADCONF 23#define OFF_PD (1 << 12) 24#define OFF_PU (3 << 12) 25#define OFF_OUT_PTD (0 << 10) 26#define OFF_OUT_PTU (2 << 10) 27#define OFF_IN (1 << 10) 28#define OFF_OUT (0 << 10) 29#define OFF_EN (1 << 9) 30#else 31#define OFF_PD (0 << 12) 32#define OFF_PU (0 << 12) 33#define OFF_OUT_PTD (0 << 10) 34#define OFF_OUT_PTU (0 << 10) 35#define OFF_IN (0 << 10) 36#define OFF_OUT (0 << 10) 37#define OFF_EN (0 << 9) 38#endif 39 40#define IEN (1 << 8) 41#define IDIS (0 << 8) 42#define PTU (3 << 3) 43#define PTD (1 << 3) 44#define EN (1 << 3) 45#define DIS (0 << 3) 46 47#define M0 0 48#define M1 1 49#define M2 2 50#define M3 3 51#define M4 4 52#define M5 5 53#define M6 6 54#define M7 7 55 56#define SAFE_MODE M7 57 58#ifdef CONFIG_OFF_PADCONF 59#define OFF_IN_PD (OFF_PD | OFF_IN | OFF_EN) 60#define OFF_IN_PU (OFF_PU | OFF_IN | OFF_EN) 61#define OFF_OUT_PD (OFF_OUT_PTD | OFF_OUT | OFF_EN) 62#define OFF_OUT_PU (OFF_OUT_PTU | OFF_OUT | OFF_EN) 63#else 64#define OFF_IN_PD 0 65#define OFF_IN_PU 0 66#define OFF_OUT_PD 0 67#define OFF_OUT_PU 0 68#endif 69 70#define CORE_REVISION 0x0000 71#define CORE_HWINFO 0x0004 72#define CORE_SYSCONFIG 0x0010 73#define GPMC_AD0 0x0040 74#define GPMC_AD1 0x0042 75#define GPMC_AD2 0x0044 76#define GPMC_AD3 0x0046 77#define GPMC_AD4 0x0048 78#define GPMC_AD5 0x004A 79#define GPMC_AD6 0x004C 80#define GPMC_AD7 0x004E 81#define GPMC_AD8 0x0050 82#define GPMC_AD9 0x0052 83#define GPMC_AD10 0x0054 84#define GPMC_AD11 0x0056 85#define GPMC_AD12 0x0058 86#define GPMC_AD13 0x005A 87#define GPMC_AD14 0x005C 88#define GPMC_AD15 0x005E 89#define GPMC_A16 0x0060 90#define GPMC_A17 0x0062 91#define GPMC_A18 0x0064 92#define GPMC_A19 0x0066 93#define GPMC_A20 0x0068 94#define GPMC_A21 0x006A 95#define GPMC_A22 0x006C 96#define GPMC_A23 0x006E 97#define GPMC_A24 0x0070 98#define GPMC_A25 0x0072 99#define GPMC_NCS0 0x0074 100#define GPMC_NCS1 0x0076 101#define GPMC_NCS2 0x0078 102#define GPMC_NCS3 0x007A 103#define GPMC_NWP 0x007C 104#define GPMC_CLK 0x007E 105#define GPMC_NADV_ALE 0x0080 106#define GPMC_NOE 0x0082 107#define GPMC_NWE 0x0084 108#define GPMC_NBE0_CLE 0x0086 109#define GPMC_NBE1 0x0088 110#define GPMC_WAIT0 0x008A 111#define GPMC_WAIT1 0x008C 112#define C2C_DATA11 0x008E 113#define C2C_DATA12 0x0090 114#define C2C_DATA13 0x0092 115#define C2C_DATA14 0x0094 116#define C2C_DATA15 0x0096 117#define HDMI_HPD 0x0098 118#define HDMI_CEC 0x009A 119#define HDMI_DDC_SCL 0x009C 120#define HDMI_DDC_SDA 0x009E 121#define CSI21_DX0 0x00A0 122#define CSI21_DY0 0x00A2 123#define CSI21_DX1 0x00A4 124#define CSI21_DY1 0x00A6 125#define CSI21_DX2 0x00A8 126#define CSI21_DY2 0x00AA 127#define CSI21_DX3 0x00AC 128#define CSI21_DY3 0x00AE 129#define CSI21_DX4 0x00B0 130#define CSI21_DY4 0x00B2 131#define CSI22_DX0 0x00B4 132#define CSI22_DY0 0x00B6 133#define CSI22_DX1 0x00B8 134#define CSI22_DY1 0x00BA 135#define CAM_SHUTTER 0x00BC 136#define CAM_STROBE 0x00BE 137#define CAM_GLOBALRESET 0x00C0 138#define USBB1_ULPITLL_CLK 0x00C2 139#define USBB1_ULPITLL_STP 0x00C4 140#define USBB1_ULPITLL_DIR 0x00C6 141#define USBB1_ULPITLL_NXT 0x00C8 142#define USBB1_ULPITLL_DAT0 0x00CA 143#define USBB1_ULPITLL_DAT1 0x00CC 144#define USBB1_ULPITLL_DAT2 0x00CE 145#define USBB1_ULPITLL_DAT3 0x00D0 146#define USBB1_ULPITLL_DAT4 0x00D2 147#define USBB1_ULPITLL_DAT5 0x00D4 148#define USBB1_ULPITLL_DAT6 0x00D6 149#define USBB1_ULPITLL_DAT7 0x00D8 150#define USBB1_HSIC_DATA 0x00DA 151#define USBB1_HSIC_STROBE 0x00DC 152#define USBC1_ICUSB_DP 0x00DE 153#define USBC1_ICUSB_DM 0x00E0 154#define SDMMC1_CLK 0x00E2 155#define SDMMC1_CMD 0x00E4 156#define SDMMC1_DAT0 0x00E6 157#define SDMMC1_DAT1 0x00E8 158#define SDMMC1_DAT2 0x00EA 159#define SDMMC1_DAT3 0x00EC 160#define SDMMC1_DAT4 0x00EE 161#define SDMMC1_DAT5 0x00F0 162#define SDMMC1_DAT6 0x00F2 163#define SDMMC1_DAT7 0x00F4 164#define ABE_MCBSP2_CLKX 0x00F6 165#define ABE_MCBSP2_DR 0x00F8 166#define ABE_MCBSP2_DX 0x00FA 167#define ABE_MCBSP2_FSX 0x00FC 168#define ABE_MCBSP1_CLKX 0x00FE 169#define ABE_MCBSP1_DR 0x0100 170#define ABE_MCBSP1_DX 0x0102 171#define ABE_MCBSP1_FSX 0x0104 172#define ABE_PDM_UL_DATA 0x0106 173#define ABE_PDM_DL_DATA 0x0108 174#define ABE_PDM_FRAME 0x010A 175#define ABE_PDM_LB_CLK 0x010C 176#define ABE_CLKS 0x010E 177#define ABE_DMIC_CLK1 0x0110 178#define ABE_DMIC_DIN1 0x0112 179#define ABE_DMIC_DIN2 0x0114 180#define ABE_DMIC_DIN3 0x0116 181#define UART2_CTS 0x0118 182#define UART2_RTS 0x011A 183#define UART2_RX 0x011C 184#define UART2_TX 0x011E 185#define HDQ_SIO 0x0120 186#define I2C1_SCL 0x0122 187#define I2C1_SDA 0x0124 188#define I2C2_SCL 0x0126 189#define I2C2_SDA 0x0128 190#define I2C3_SCL 0x012A 191#define I2C3_SDA 0x012C 192#define I2C4_SCL 0x012E 193#define I2C4_SDA 0x0130 194#define MCSPI1_CLK 0x0132 195#define MCSPI1_SOMI 0x0134 196#define MCSPI1_SIMO 0x0136 197#define MCSPI1_CS0 0x0138 198#define MCSPI1_CS1 0x013A 199#define MCSPI1_CS2 0x013C 200#define MCSPI1_CS3 0x013E 201#define UART3_CTS_RCTX 0x0140 202#define UART3_RTS_SD 0x0142 203#define UART3_RX_IRRX 0x0144 204#define UART3_TX_IRTX 0x0146 205#define SDMMC5_CLK 0x0148 206#define SDMMC5_CMD 0x014A 207#define SDMMC5_DAT0 0x014C 208#define SDMMC5_DAT1 0x014E 209#define SDMMC5_DAT2 0x0150 210#define SDMMC5_DAT3 0x0152 211#define MCSPI4_CLK 0x0154 212#define MCSPI4_SIMO 0x0156 213#define MCSPI4_SOMI 0x0158 214#define MCSPI4_CS0 0x015A 215#define UART4_RX 0x015C 216#define UART4_TX 0x015E 217#define USBB2_ULPITLL_CLK 0x0160 218#define USBB2_ULPITLL_STP 0x0162 219#define USBB2_ULPITLL_DIR 0x0164 220#define USBB2_ULPITLL_NXT 0x0166 221#define USBB2_ULPITLL_DAT0 0x0168 222#define USBB2_ULPITLL_DAT1 0x016A 223#define USBB2_ULPITLL_DAT2 0x016C 224#define USBB2_ULPITLL_DAT3 0x016E 225#define USBB2_ULPITLL_DAT4 0x0170 226#define USBB2_ULPITLL_DAT5 0x0172 227#define USBB2_ULPITLL_DAT6 0x0174 228#define USBB2_ULPITLL_DAT7 0x0176 229#define USBB2_HSIC_DATA 0x0178 230#define USBB2_HSIC_STROBE 0x017A 231#define UNIPRO_TX0 0x017C 232#define UNIPRO_TY0 0x017E 233#define UNIPRO_TX1 0x0180 234#define UNIPRO_TY1 0x0182 235#define UNIPRO_TX2 0x0184 236#define UNIPRO_TY2 0x0186 237#define UNIPRO_RX0 0x0188 238#define UNIPRO_RY0 0x018A 239#define UNIPRO_RX1 0x018C 240#define UNIPRO_RY1 0x018E 241#define UNIPRO_RX2 0x0190 242#define UNIPRO_RY2 0x0192 243#define USBA0_OTG_CE 0x0194 244#define USBA0_OTG_DP 0x0196 245#define USBA0_OTG_DM 0x0198 246#define FREF_CLK1_OUT 0x019A 247#define FREF_CLK2_OUT 0x019C 248#define SYS_NIRQ1 0x019E 249#define SYS_NIRQ2 0x01A0 250#define SYS_BOOT0 0x01A2 251#define SYS_BOOT1 0x01A4 252#define SYS_BOOT2 0x01A6 253#define SYS_BOOT3 0x01A8 254#define SYS_BOOT4 0x01AA 255#define SYS_BOOT5 0x01AC 256#define DPM_EMU0 0x01AE 257#define DPM_EMU1 0x01B0 258#define DPM_EMU2 0x01B2 259#define DPM_EMU3 0x01B4 260#define DPM_EMU4 0x01B6 261#define DPM_EMU5 0x01B8 262#define DPM_EMU6 0x01BA 263#define DPM_EMU7 0x01BC 264#define DPM_EMU8 0x01BE 265#define DPM_EMU9 0x01C0 266#define DPM_EMU10 0x01C2 267#define DPM_EMU11 0x01C4 268#define DPM_EMU12 0x01C6 269#define DPM_EMU13 0x01C8 270#define DPM_EMU14 0x01CA 271#define DPM_EMU15 0x01CC 272#define DPM_EMU16 0x01CE 273#define DPM_EMU17 0x01D0 274#define DPM_EMU18 0x01D2 275#define DPM_EMU19 0x01D4 276#define WAKEUPEVENT_0 0x01D8 277#define WAKEUPEVENT_1 0x01DC 278#define WAKEUPEVENT_2 0x01E0 279#define WAKEUPEVENT_3 0x01E4 280#define WAKEUPEVENT_4 0x01E8 281#define WAKEUPEVENT_5 0x01EC 282#define WAKEUPEVENT_6 0x01F0 283 284#define WKUP_REVISION 0x0000 285#define WKUP_HWINFO 0x0004 286#define WKUP_SYSCONFIG 0x0010 287#define PAD0_SIM_IO 0x0040 288#define PAD1_SIM_CLK 0x0042 289#define PAD0_SIM_RESET 0x0044 290#define PAD1_SIM_CD 0x0046 291#define PAD0_SIM_PWRCTRL 0x0048 292#define PAD1_SR_SCL 0x004A 293#define PAD0_SR_SDA 0x004C 294#define PAD1_FREF_XTAL_IN 0x004E 295#define PAD0_FREF_SLICER_IN 0x0050 296#define PAD1_FREF_CLK_IOREQ 0x0052 297#define PAD0_FREF_CLK0_OUT 0x0054 298#define PAD1_FREF_CLK3_REQ 0x0056 299#define PAD0_FREF_CLK3_OUT 0x0058 300#define PAD1_FREF_CLK4_REQ 0x005A 301#define PAD0_FREF_CLK4_OUT 0x005C 302#define PAD1_SYS_32K 0x005E 303#define PAD0_SYS_NRESPWRON 0x0060 304#define PAD1_SYS_NRESWARM 0x0062 305#define PAD0_SYS_PWR_REQ 0x0064 306#define PAD1_SYS_PWRON_RESET 0x0066 307#define PAD0_SYS_BOOT6 0x0068 308#define PAD1_SYS_BOOT7 0x006A 309#define PAD0_JTAG_NTRST 0x006C 310#define PAD1_JTAG_TCK 0x006D 311#define PAD0_JTAG_RTCK 0x0070 312#define PAD1_JTAG_TMS_TMSC 0x0072 313#define PAD0_JTAG_TDI 0x0074 314#define PAD1_JTAG_TDO 0x0076 315#define PADCONF_WAKEUPEVENT_0 0x007C 316#define CONTROL_SMART1NOPMIO_PADCONF_0 0x05A0 317#define CONTROL_SMART1NOPMIO_PADCONF_1 0x05A4 318#define PADCONF_MODE 0x05A8 319#define CONTROL_XTAL_OSCILLATOR 0x05AC 320#define CONTROL_CONTROL_I2C_2 0x0604 321#define CONTROL_CONTROL_JTAG 0x0608 322#define CONTROL_CONTROL_SYS 0x060C 323#define CONTROL_SPARE_RW 0x0614 324#define CONTROL_SPARE_R 0x0618 325#define CONTROL_SPARE_R_C0 0x061C 326 327#define CONTROL_WKUP_PAD1_FREF_CLK4_REQ 0x4A31E05A 328#endif /* _MUX_OMAP4_H_ */ 329