1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <asm/arch/gpio.h>
7#include <asm/fsp1/fsp_support.h>
8
9static const struct gpio_family gpio_family[] = {
10	GPIO_FAMILY_CONF("SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0", NA, 0,
11			 VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),
12
13	/* end of the table */
14	GPIO_FAMILY_CONF("GPIO FAMILY TABLE END", NA, 0,
15			 VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),
16};
17
18static const struct gpio_pad gpio_pad[] = {
19	GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
20		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
21		      NA, 29, NA, 0x4c38, NORTH),
22	GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
23		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
24		      NA, 27, NA, 0x4c28, NORTH),
25	GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
26		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
27		      NA, 20, NA, 0x4858, NORTH),
28	GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
29		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
30		      NA, 37, NA, 0x5018, NORTH),
31	GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
32		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
33		      NA, 42, NA, 0x5040, NORTH),
34	GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
35		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
36		      NA, 35, NA, 0x5008, NORTH),
37	GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
38		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
39		      NA, 40, NA, 0x5030, NORTH),
40	GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
41		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
42		      NA, 45, NA, 0x5058, NORTH),
43	GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
44		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
45		      NA, 34, NA, 0x5000, NORTH),
46	GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GPO, LOW,
47		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
48		      NA, 38, NA, 0x5020, NORTH),
49	GPIO_PAD_CONF("N54: GP_CAMERASB07", GPIO, M1, GPO, LOW,
50		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
51		      NA, 43, NA, 0x5048, NORTH),
52	GPIO_PAD_CONF("N47: GP_CAMERASB08", GPIO, M1, GPO, LOW,
53		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
54		      NA, 36, NA, 0x5010, NORTH),
55	GPIO_PAD_CONF("N52: GP_CAMERASB09", GPIO, M1, GPO, LOW,
56		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
57		      NA, 41, NA, 0x5038, NORTH),
58	GPIO_PAD_CONF("N50: GP_CAMERASB10", GPIO, M1, GPO, LOW,
59		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
60		      NA, 39, NA, 0x5028, NORTH),
61	GPIO_PAD_CONF("N55: GP_CAMERASB11", GPIO, M1, GPO, LOW,
62		      NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
63		      NA, 44, NA, 0x5050, NORTH),
64	GPIO_PAD_CONF("N00: GPIO_DFX0", NATIVE, M5, NA, NA, NA,
65		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
66		      NA, 0, NA, 0x4400, NORTH),
67	GPIO_PAD_CONF("N03: GPIO_DFX1", NATIVE, M5, NA, NA, NA,
68		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
69		      NA, 3, NA, 0x4418, NORTH),
70	GPIO_PAD_CONF("N07: GPIO_DFX2", NATIVE, M5, NA, NA, NA,
71		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
72		      NA, 2, NA, 0x4438, NORTH),
73	GPIO_PAD_CONF("N01: GPIO_DFX3", NATIVE, M5, NA, NA, NA,
74		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
75		      NA, 1, NA, 0x4408, NORTH),
76	GPIO_PAD_CONF("N05: GPIO_DFX4", GPIO, M1, GPO, HIGH, NA,
77		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
78		      NA, 5, NA, 0x4428, NORTH),
79	GPIO_PAD_CONF("N04: GPIO_DFX5", GPIO, M1, GPO, HIGH, NA,
80		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
81		      NA, 4, NA, 0x4420, NORTH),
82	GPIO_PAD_CONF("N08: GPIO_DFX6", NATIVE, M8, NA, NA, NA,
83		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
84		      NA, 8, NA, 0x4440, NORTH),
85	GPIO_PAD_CONF("N02: GPIO_DFX7", GPIO, M1, GPO, LOW, NA,
86		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
87		      NA, 2, NA, 0x4410, NORTH),
88	GPIO_PAD_CONF("N15: GPIO_SUS0", GPIO, M1, GPI, NA, NA,
89		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
90		      NA, 9 , NA, 0x4800, NORTH),
91	GPIO_PAD_CONF("N19: GPIO_SUS1", GPIO, M1, GPI, NA, NA,
92		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
93		      NA, 13, NA, 0x4820, NORTH),
94	GPIO_PAD_CONF("N24: GPIO_SUS2", GPIO, M1, GPI, NA, NA,
95		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
96		      NA, 18, NA, 0x4848, NORTH),
97	GPIO_PAD_CONF("N17: GPIO_SUS3", NATIVE, M6, NA, NA, NA,
98		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
99		      NA, 11, NA, 0x4810, NORTH),
100	GPIO_PAD_CONF("N22: GPIO_SUS4", GPIO, M1, GPO, HIGH, NA,
101		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
102		      NA, 16, NA, 0x4838, NORTH),
103	GPIO_PAD_CONF("N20: GPIO_SUS5", GPIO, M1, GPO, HIGH, NA,
104		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
105		      NA, 14, NA, 0x4828, NORTH),
106	GPIO_PAD_CONF("N25: GPIO_SUS6", GPIO, M1, GPI, NA, NA,
107		      TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,
108		      EN_EDGE_RX_DATA, NO_INVERSION,
109		      NA, 19, SCI, 0x4850, NORTH),
110	GPIO_PAD_CONF("N18: GPIO_SUS7", GPIO, M1, GPI, NA, NA,
111		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
112		      NA, 12, SMI, 0x4818, NORTH),
113	GPIO_PAD_CONF("N71: HV_DDI0_DDC_SCL", NATIVE, M1, NA, NA, NA,
114		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
115		      NA, 57, NA, 0x5458, NORTH),
116	GPIO_PAD_CONF("N66: HV_DDI0_DDC_SDA", NATIVE, M1, NA, NA, NA,
117		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
118		      NA, 52, NA, 0x5430, NORTH),
119	GPIO_PAD_CONF("N61: HV_DDI0_HPD", NATIVE, M1, NA, NA, NA,
120		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
121		      NA, 47, NA, 0x5408, NORTH),
122	GPIO_PAD_CONF("N64: HV_DDI1_HPD", NATIVE, M1, NA, NA, NA,
123		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
124		      NA, 50, NA, 0x5420, NORTH),
125	GPIO_PAD_CONF("N67: HV_DDI2_DDC_SCL", NATIVE, M3, NA, NA, NA,
126		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
127		      NA, 53, NA, 0x5438, NORTH),
128	GPIO_PAD_CONF("N62: HV_DDI2_DDC_SDA", NATIVE, M3, NA, NA, NA,
129		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
130		      NA, 48, NA, 0x5410, NORTH),
131	GPIO_PAD_CONF("N68: HV_DDI2_HPD", NATIVE, M1, NA, NA, NA,
132		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
133		      NA, 54, NA, 0x5440, NORTH),
134	GPIO_PAD_CONF("N65: PANEL0_BKLTCTL", GPIO, M1, GPI, NA, NA,
135		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
136		      NA, 51, NA, 0x5428, NORTH),
137	GPIO_PAD_CONF("N60: PANEL0_BKLTEN", GPIO, M1, GPI, NA, NA,
138		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
139		      NA, 46, NA, 0x5400, NORTH),
140	GPIO_PAD_CONF("N72: PANEL0_VDDEN", GPIO, M1, GPI, NA, NA,
141		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
142		      NA, 58, NA, 0x5460, NORTH),
143	GPIO_PAD_CONF("N63: PANEL1_BKLTCTL", NATIVE, M1, NA, NA, NA,
144		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
145		      NA, 49, NA, 0x5418, NORTH),
146	GPIO_PAD_CONF("N70: PANEL1_BKLTEN", NATIVE, M1, NA, NA, NA,
147		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
148		      NA, 56, NA, 0x5450, NORTH),
149	GPIO_PAD_CONF("N69: PANEL1_VDDEN", NATIVE, M1, NA, NA, NA,
150		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
151		      NA, 55, NA, 0x5448, NORTH),
152	GPIO_PAD_CONF("N32: PROCHOT_B", NATIVE, M1, NA, NA, NA,
153		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
154		      NA, 24, NA, 0x4c10, NORTH),
155	GPIO_PAD_CONF("N16: SEC_GPIO_SUS10", GPIO, M1, GPI, NA, NA,
156		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
157		      NA, 10, NA, 0x4808, NORTH),
158	GPIO_PAD_CONF("N21: SEC_GPIO_SUS11", GPIO, M1, GPI, NA, NA,
159		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
160		      NA, 15, NA, 0x4830, NORTH),
161	GPIO_PAD_CONF("N23: SEC_GPIO_SUS8", GPIO, M1, GPI, NA, NA,
162		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
163		      NA, 17, NA, 0x4840, NORTH),
164	GPIO_PAD_CONF("N27: SEC_GPIO_SUS9", GPIO, M1, GPI, LOW, NA,
165		      TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,
166		      EN_RX_DATA, INV_RX_DATA,
167		      NA, 21, SCI, 0x4860, NORTH),
168	GPIO_PAD_CONF("N31: TCK", NATIVE, M1, NA, NA, NA,
169		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
170		      NA, 23, NA, 0x4c08, NORTH),
171	GPIO_PAD_CONF("N41: TDI", NATIVE, M1, NA, NA, NA,
172		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
173		      NA, 33, NA, 0x4c58, NORTH),
174	GPIO_PAD_CONF("N39: TDO", NATIVE, M1, NA, NA, NA,
175		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
176		      NA, 31, NA, 0x4c48, NORTH),
177	GPIO_PAD_CONF("N36: TDO_2", NATIVE, M1, NA, NA, NA,
178		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
179		      NA, 28, NA, 0x4c30, NORTH),
180	GPIO_PAD_CONF("N34: TMS", NATIVE, M1, NA, NA, NA,
181		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
182		      NA, 26, NA, 0x4c20, NORTH),
183	GPIO_PAD_CONF("N30: TRST_B", NATIVE, M1, NA, NA, NA,
184		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
185		      NA, 22, NA, 0x4c00, NORTH),
186
187	GPIO_PAD_CONF("E21: MF_ISH_GPIO_0", GPIO, M1, GPI, NA, NA,
188		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
189		      NA, 18, NA, 0x4830, EAST),
190	GPIO_PAD_CONF("E18: MF_ISH_GPIO_1", GPIO, M1, GPI, NA, NA,
191		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
192		      NA, 15, NA, 0x4818, EAST),
193	GPIO_PAD_CONF("E24: MF_ISH_GPIO_2", GPIO, M1, GPI, NA, NA,
194		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
195		      NA, 21, NA, 0x4848, EAST),
196	GPIO_PAD_CONF("E15: MF_ISH_GPIO_3", GPIO, M1, GPI, NA, NA,
197		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
198		      NA, 12, NA, 0x4800, EAST),
199	GPIO_PAD_CONF("E22: MF_ISH_GPIO_4", GPIO, M1, GPI, NA, NA,
200		      NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,
201		      NA, 19, NA, 0x4838, EAST),
202	GPIO_PAD_CONF("E19: MF_ISH_GPIO_5", GPIO, M1, GPO, HIGH, NA,
203		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
204		      NA, 16, NA, 0x4820, EAST),
205	GPIO_PAD_CONF("E25: MF_ISH_GPIO_6", NATIVE, M1, NA, NA, NA,
206		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
207		      NA, 22, NA, 0x4850, EAST),
208	GPIO_PAD_CONF("E16: MF_ISH_GPIO_7", GPIO, M1, GPO, HIGH, NA,
209		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
210		      NA, 13, NA, 0x4808, EAST),
211	GPIO_PAD_CONF("E23: MF_ISH_GPIO_8", NATIVE, M1, NA, NA, NA,
212		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
213		      NA, 20, NA, 0x4840, EAST),
214	GPIO_PAD_CONF("E20: MF_ISH_GPIO_9", NATIVE, M1, NA, NA, NA,
215		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
216		      NA, 17, NA, 0x4828, EAST),
217	GPIO_PAD_CONF("E26: MF_ISH_I2C1_SDA", NATIVE, M1, NA, NA, NA,
218		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
219		      NA, 23, NA, 0x4858, EAST),
220	GPIO_PAD_CONF("E17: MF_ISH_I2C1_SCL", NATIVE, M1, NA, NA, NA,
221		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
222		      NA, 14, NA, 0x4810, EAST),
223	GPIO_PAD_CONF("E04: PMU_AC_PRESENT", NATIVE, M1, NA, NA, NA,
224		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
225		      NA, 4, NA, 0x4420, EAST),
226	GPIO_PAD_CONF("E01: PMU_BATLOW_B", NATIVE, M1, NA, NA, NA,
227		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
228		      NA, 1, NA, 0x4408, EAST),
229	GPIO_PAD_CONF("E05: PMU_PLTRST_B", NATIVE, M1, NA, NA, NA,
230		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
231		      NA, 5, NA, 0x4428, EAST),
232	GPIO_PAD_CONF("E07: PMU_SLP_LAN_B", NATIVE, M1, NA, NA, NA,
233		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
234		      NA, 7, NA, 0x4438, EAST),
235	GPIO_PAD_CONF("E03: PMU_SLP_S0IX_B", NATIVE, M1, NA, NA, NA,
236		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
237		      NA, 3, NA, 0x4418, EAST),
238	GPIO_PAD_CONF("E00: PMU_SLP_S3_B", NATIVE, M1, NA, NA, NA,
239		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
240		      NA, 0, NA, 0x4400, EAST),
241	GPIO_PAD_CONF("E09: PMU_SLP_S4_B", NATIVE, M1, NA, NA, NA,
242		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
243		      NA, 9, NA, 0x4448, EAST),
244	GPIO_PAD_CONF("E06: PMU_SUSCLK", NATIVE, M1, NA, NA, NA,
245		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
246		      NA, 6, NA, 0x4430, EAST),
247	GPIO_PAD_CONF("E10: PMU_WAKE_B", NATIVE, M1, NA, NA, NA,
248		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
249		      NA, 10, NA, 0x4450, EAST),
250	GPIO_PAD_CONF("E11: PMU_WAKE_LAN_B", NATIVE, M1, NA, NA, NA,
251		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
252		      NA, 11, NA, 0x4458, EAST),
253	GPIO_PAD_CONF("E02: SUS_STAT_B", NATIVE, M1, NA, NA, NA,
254		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
255		      NA, 2, NA, 0x4410, EAST),
256
257	GPIO_PAD_CONF("SE16: SDMMC1_CLK", NATIVE, M1, NA, NA, HIGH,
258		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
259		      NA, 9, NA, 0x4808, SOUTHEAST),
260	GPIO_PAD_CONF("SE23: SDMMC1_CMD", NATIVE, M1, NA, NA, HIGH,
261		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
262		      NA, 16, NA, 0x4840, SOUTHEAST),
263	GPIO_PAD_CONF("SE17: SDMMC1_D0", NATIVE, M1, NA, NA, HIGH,
264		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
265		      NA, 10, NA, 0x4810, SOUTHEAST),
266	GPIO_PAD_CONF("SE24: SDMMC1_D1", NATIVE, M1, NA, NA, HIGH,
267		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
268		      NA, 17, NA, 0x4848, SOUTHEAST),
269	GPIO_PAD_CONF("SE20: SDMMC1_D2", NATIVE, M1, NA, NA, HIGH,
270		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
271		      NA, 13, NA, 0x4828, SOUTHEAST),
272	GPIO_PAD_CONF("SE26: SDMMC1_D3_CD_B", NATIVE, M1, NA, NA, HIGH,
273		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
274		      NA, 19, NA, 0x4858, SOUTHEAST),
275	GPIO_PAD_CONF("SE67: MMC1_D4_SD_WE", NATIVE, M1, NA, NA, HIGH,
276		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
277		      NA, 41, NA, 0x5438, SOUTHEAST),
278	GPIO_PAD_CONF("SE65: MMC1_D5", NATIVE, M1, NA, NA, HIGH,
279		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
280		      NA, 39, NA, 0x5428, SOUTHEAST),
281	GPIO_PAD_CONF("SE63: MMC1_D6", NATIVE, M1, NA, NA, HIGH,
282		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
283		      NA, 37, NA, 0x5418, SOUTHEAST),
284	GPIO_PAD_CONF("SE68: MMC1_D7", NATIVE, M1, NA, NA, HIGH,
285		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
286		      NA, 42, NA, 0x5440, SOUTHEAST),
287	GPIO_PAD_CONF("SE69: MMC1_RCLK", NATIVE, M1, NA, NA, NA,
288		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
289		      NA, 43, NA, 0x5448, SOUTHEAST),
290	GPIO_PAD_CONF("SE77: GPIO_ALERT", GPIO, M1, GPI, NA, NA,
291		      TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,
292		      EN_RX_DATA, INV_RX_DATA,
293		      NA, 46, NA, 0x5810, SOUTHEAST),
294	GPIO_PAD_CONF("SE79: ILB_SERIRQ", NATIVE, M1, NA, NA, NA,
295		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
296		      NA, 48, NA, 0x5820, SOUTHEAST),
297	GPIO_PAD_CONF("SE51: MF_LPC_CLKOUT0", NATIVE, M1, NA, NA, NA,
298		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
299		      NA, 32, NA, 0x5030, SOUTHEAST),
300	GPIO_PAD_CONF("SE49: MF_LPC_CLKOUT1", NATIVE, M1, NA, NA, NA,
301		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
302		      NA, 30, NA, 0x5020, SOUTHEAST),
303	GPIO_PAD_CONF("SE47: MF_LPC_AD0", NATIVE, M1, NA, NA, NA,
304		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
305		      NA, 28, NA, 0x5010, SOUTHEAST),
306	GPIO_PAD_CONF("SE52: MF_LPC_AD1", NATIVE, M1, NA, NA, NA,
307		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
308		      NA, 33, NA, 0x5038, SOUTHEAST),
309	GPIO_PAD_CONF("SE45: MF_LPC_AD2", NATIVE, M1, NA, NA, NA,
310		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
311		      NA, 26, NA, 0x5000, SOUTHEAST),
312	GPIO_PAD_CONF("SE50: MF_LPC_AD3", NATIVE, M1, NA, NA, NA,
313		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
314		      NA, 31, NA, 0x5028, SOUTHEAST),
315	GPIO_PAD_CONF("SE46: LPC_CLKRUNB", NATIVE, M1, NA, NA, NA,
316		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
317		      NA, 27, NA, 0x5008, SOUTHEAST),
318	GPIO_PAD_CONF("SE48: LPC_FRAMEB", NATIVE, M1, NA, NA, NA,
319		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
320		      NA, 29, NA, 0x5018, SOUTHEAST),
321	GPIO_PAD_CONF("SE00: MF_PLT_CLK0", NATIVE, M1, NA, NA, NA,
322		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
323		      NA, 0, NA, 0x4400, SOUTHEAST),
324	GPIO_PAD_CONF("SE02: MF_PLT_CLK1", NATIVE, M1, NA, NA, NA,
325		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
326		      NA, 1, NA, 0x4410, SOUTHEAST),
327	GPIO_PAD_CONF("SE07: MF_PLT_CLK2", GPIO, M1, GPI, NA, NA,
328		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
329		      NA, 7, NA, 0x4438, SOUTHEAST),
330	GPIO_PAD_CONF("SE04: MF_PLT_CLK3", GPIO, M1, GPI, NA, NA,
331		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
332		      NA, 4, NA, 0x4420, SOUTHEAST),
333	GPIO_PAD_CONF("SE03: MF_PLT_CLK4", GPIO, M1, GPO, LOW, NA,
334		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
335		      NA, 3, NA, 0x4418, SOUTHEAST),
336	GPIO_PAD_CONF("SE06: MF_PLT_CLK5", GPIO, M3, GPO, LOW, NA,
337		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
338		      NA, 6, NA, 0x4430, SOUTHEAST),
339	GPIO_PAD_CONF("SE83: SUSPWRDNACK", NATIVE, M1, NA, NA, NA,
340		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
341		      NA, 52, NA, 0x5840, SOUTHEAST),
342	GPIO_PAD_CONF("SE05: PWM0", GPIO, M1, GPO, LOW, NA,
343		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
344		      NA, 5, NA, 0x4428, SOUTHEAST),
345	GPIO_PAD_CONF("SE01: PWM1", GPIO, M1, GPO, HIGH, NA,
346		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
347		      NA, 1, NA, 0x4408, SOUTHEAST),
348	GPIO_PAD_CONF("SE85: SDMMC3_1P8_EN", NATIVE, M1, NA, NA, NA,
349		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
350		      NA, 54, NA, 0x5850, SOUTHEAST),
351	GPIO_PAD_CONF("SE81: SDMMC3_CD_B", NATIVE, M1, NA, NA, NA,
352		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
353		      NA, 50, NA, 0x5830, SOUTHEAST),
354	GPIO_PAD_CONF("SE31: SDMMC3_CLK", NATIVE, M1, NA, NA, NA,
355		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
356		      NA, 21, NA, 0x4c08, SOUTHEAST),
357	GPIO_PAD_CONF("SE34: SDMMC3_CMD", NATIVE, M1, NA, NA, NA,
358		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
359		      NA, 24, NA, 0x4c20, SOUTHEAST),
360	GPIO_PAD_CONF("SE35: SDMMC3_D0", NATIVE, M1, NA, NA, NA,
361		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
362		      NA, 25, NA, 0x4c28, SOUTHEAST),
363	GPIO_PAD_CONF("SE30: SDMMC3_D1", NATIVE, M1, NA, NA, NA,
364		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
365		      NA, 20, NA, 0x4c00, SOUTHEAST),
366	GPIO_PAD_CONF("SE33: SDMMC3_D2", NATIVE, M1, NA, NA, NA,
367		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
368		      NA, 23, NA, 0x4c18, SOUTHEAST),
369	GPIO_PAD_CONF("SE32: SDMMC3_D3", NATIVE, M1, NA, NA, NA,
370		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
371		      NA, 22, NA, 0x4c10, SOUTHEAST),
372	GPIO_PAD_CONF("SE78: SDMMC3_PWR_EN_B", NATIVE, M1, NA, NA, NA,
373		      NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,
374		      NA, 47, NA, 0x5818, SOUTHEAST),
375	GPIO_PAD_CONF("SE19: SDMMC2_CLK", NATIVE, M1, NA, NA, NA,
376		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
377		      NA, 12, NA, 0x4820, SOUTHEAST),
378	GPIO_PAD_CONF("SE22: SDMMC2_CMD", NATIVE, M1, NA, NA, NA,
379		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
380		      NA, 15, NA, 0x4838, SOUTHEAST),
381	GPIO_PAD_CONF("SE25: SDMMC2_D0", NATIVE, M1, NA, NA, NA,
382		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
383		      NA, 18, NA, 0x4850, SOUTHEAST),
384	GPIO_PAD_CONF("SE18: SDMMC2_D1", NATIVE, M1, NA, NA, NA,
385		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
386		      NA, 11, NA, 0x4818, SOUTHEAST),
387	GPIO_PAD_CONF("SE21: SDMMC2_D2", NATIVE, M1, NA, NA, NA,
388		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
389		      NA, 14, NA, 0x4830, SOUTHEAST),
390	GPIO_PAD_CONF("SE15: SDMMC2_D3_CD_B", NATIVE, M1, NA, NA, NA,
391		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
392		      NA, 8, NA, 0x4800, SOUTHEAST),
393	GPIO_PAD_CONF("SE62: SPI1_CLK", NATIVE, M1, NA, NA, NA,
394		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
395		      NA, 36, NA, 0x5410, SOUTHEAST),
396	GPIO_PAD_CONF("SE61: SPI1_CS0_B", NATIVE, M1, NA, NA, NA,
397		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
398		      NA, 35, NA, 0x5408, SOUTHEAST),
399	GPIO_PAD_CONF("SE66: SPI1_CS1_B", NATIVE, M1, NA, NA, NA,
400		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
401		      NA, 40, NA, 0x5430, SOUTHEAST),
402	GPIO_PAD_CONF("SE60: SPI1_MISO", NATIVE, M1, NA, NA, NA,
403		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
404		      NA, 34, NA, 0x5400, SOUTHEAST),
405	GPIO_PAD_CONF("SE64: SPI1_MOSI", NATIVE, M1, NA, NA, NA,
406		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
407		      NA, 38, NA, 0x5420, SOUTHEAST),
408	GPIO_PAD_CONF("SE80: USB_OC0_B", NATIVE, M1, NA, NA, NA,
409		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
410		      NA, 49, NA, 0x5828, SOUTHEAST),
411	GPIO_PAD_CONF("SE75: USB_OC1_B", NATIVE, M1, NA, NA, NA,
412		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
413		      NA, 44, NA, 0x5800, SOUTHEAST),
414	GPIO_PAD_CONF("SW02: FST_SPI_CLK", NATIVE, M1, NA, NA, NA,
415		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
416		      NA, 2, NA, 0x4410, SOUTHWEST),
417	GPIO_PAD_CONF("SW06: FST_SPI_CS0_B", NATIVE, M1, NA, NA, NA,
418		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
419		      NA, 6, NA, 0x4430, SOUTHWEST),
420	GPIO_PAD_CONF("SW04: FST_SPI_CS1_B", GPIO, M1, GPO, HIGH, NA,
421		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
422		      NA, 4, NA, 0x4420, SOUTHWEST),
423	GPIO_PAD_CONF("SW07: FST_SPI_CS2_B", GPIO, M1, GPO, LOW, NA,
424		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
425		      NA, 7, NA, 0x4438, SOUTHWEST),
426	GPIO_PAD_CONF("SW01: FST_SPI_D0", NATIVE, M1, NA, NA, NA,
427		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
428		      NA, 1, NA, 0x4408, SOUTHWEST),
429	GPIO_PAD_CONF("SW05: FST_SPI_D1", NATIVE, M1, NA, NA, NA,
430		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
431		      NA, 5, NA, 0x4428, SOUTHWEST),
432	GPIO_PAD_CONF("SW00: FST_SPI_D2", NATIVE, M1, NA, NA, NA,
433		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
434		      NA, 0, NA, 0x4400, SOUTHWEST),
435	GPIO_PAD_CONF("SW03: FST_SPI_D3", NATIVE, M1, NA, NA, NA,
436		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
437		      NA, 3, NA, 0x4418, SOUTHWEST),
438	GPIO_PAD_CONF("SW30: MF_HDA_CLK", NATIVE, M2, NA, NA, NA,
439		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
440		      NA, 16, NA, 0x4c00, SOUTHWEST),
441	GPIO_PAD_CONF("SW37: MF_HDA_DOCKENB", NATIVE, M1, NA, NA, NA,
442		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
443		      NA, 23, NA, 0x4c38, SOUTHWEST),
444	GPIO_PAD_CONF("SW34: MF_HDA_DOCKRSTB", NATIVE, M1, NA, NA, NA,
445		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
446		      NA, 20, NA, 0x4c20, SOUTHWEST),
447	GPIO_PAD_CONF("SW31: MF_HDA_RSTB", NATIVE, M2, NA, NA, NA,
448		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
449		      NA, 17, NA, 0x4c08, SOUTHWEST),
450	GPIO_PAD_CONF("SW32: MF_HDA_SDI0", NATIVE, M2, NA, NA, NA,
451		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
452		      NA, 18, NA, 0x4c10, SOUTHWEST),
453	GPIO_PAD_CONF("SW36: MF_HDA_SDI1", NATIVE, M2, NA, NA, NA,
454		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
455		      NA, 22, NA, 0x4c30, SOUTHWEST),
456	GPIO_PAD_CONF("SW33: MF_HDA_SDO", NATIVE, M2, NA, NA, NA,
457		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
458		      NA, 19, NA, 0x4c18, SOUTHWEST),
459	GPIO_PAD_CONF("SW35: MF_HDA_SYNC", NATIVE, M2, NA, NA, NA,
460		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
461		      NA, 21, NA, 0x4c28, SOUTHWEST),
462	GPIO_PAD_CONF("SW18: UART1_CTS_B", NATIVE, M1, NA, NA, NA,
463		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
464		      NA, 11, NA, 0x4818, SOUTHWEST),
465	GPIO_PAD_CONF("SW15: UART1_RTS_B", NATIVE, M1, NA, NA, NA,
466		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
467		      NA, 8, NA, 0x4800, SOUTHWEST),
468	GPIO_PAD_CONF("SW16: UART1_RXD", NATIVE, M1, NA, NA, NA,
469		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
470		      NA, 9, NA, 0x4808, SOUTHWEST),
471	GPIO_PAD_CONF("SW20: UART1_TXD", NATIVE, M1, NA, NA, NA,
472		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
473		      NA, 13, NA, 0x4828, SOUTHWEST),
474	GPIO_PAD_CONF("SW22: UART2_CTS_B", NATIVE, M1, NA, NA, NA,
475		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
476		      NA, 15, NA, 0x4838, SOUTHWEST),
477	GPIO_PAD_CONF("SW19: UART2_RTS_B", NATIVE, M1, NA, NA, NA,
478		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
479		      NA, 12, NA, 0x4820, SOUTHWEST),
480	GPIO_PAD_CONF("SW17: UART2_RXD", NATIVE, M1, NA, NA, NA,
481		      NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,
482		      NA, 10, NA, 0x4810, SOUTHWEST),
483	GPIO_PAD_CONF("SW21: UART2_TXD", NATIVE, M1, NA, NA, NA,
484		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
485		      NA, 14, NA, 0x4830, SOUTHWEST),
486	GPIO_PAD_CONF("SW50: I2C4_SCL", NATIVE, M3, NA, NA, NA,
487		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
488		      NA, 29, NA, 0x5028, SOUTHWEST),
489	GPIO_PAD_CONF("SW46: I2C4_SDA", NATIVE, M3, NA, NA, NA,
490		      NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,
491		      NA, 25, NA, 0x5008, SOUTHWEST),
492	GPIO_PAD_CONF("SW49: I2C_NFC_SDA", NATIVE, M1, NA, NA, NA,
493		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
494		      NA, 28, NA, 0x5020, SOUTHWEST),
495	GPIO_PAD_CONF("SW52: I2C_NFC_SCL", NATIVE, M1, NA, NA, NA,
496		      NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,
497		      NA, 31, NA, 0x5038, SOUTHWEST),
498	GPIO_PAD_CONF("SW77: GP_SSP_2_CLK", NATIVE, M1, NA, NA, NA,
499		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
500		      NA, 50, NA, 0x5c10, SOUTHWEST),
501	GPIO_PAD_CONF("SW81: GP_SSP_2_FS", NATIVE, M1, NA, NA, NA,
502		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
503		      NA, 54, NA, 0x5c30, SOUTHWEST),
504	GPIO_PAD_CONF("SW79: GP_SSP_2_RXD", NATIVE, M1, NA, NA, NA,
505		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
506		      NA, 52, NA, 0x5c20, SOUTHWEST),
507	GPIO_PAD_CONF("SW82: GP_SSP_2_TXD", NATIVE, M1, NA, NA, NA,
508		      NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,
509		      NA, 55, NA, 0x5C38, SOUTHWEST),
510	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
511		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
512		      NA, 48, NA, 0x5c00, SOUTHWEST),
513	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
514		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
515		      NA, 49, NA, 0x5c08, SOUTHWEST),
516	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
517		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
518		      NA, 51, NA, 0x5c18, SOUTHWEST),
519	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
520		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
521		      NA, 53, NA, 0x5c28, SOUTHWEST),
522	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA,
523		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
524		      NA, 40, NA, 0x5800, SOUTHWEST),
525	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA,
526		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
527		      NA, 41, NA, 0x5808, SOUTHWEST),
528	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
529		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
530		      NA, 43, NA, 0x5818, SOUTHWEST),
531	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
532		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
533		      NA, 45, NA, 0x5828, SOUTHWEST),
534	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
535		      NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,
536		      NA, 42, NA, 0x5810, SOUTHWEST),
537	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
538		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
539		      NA, 44, NA, 0x5820, SOUTHWEST),
540	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
541		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
542		      NA, 46, NA, 0x5830, SOUTHWEST),
543	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
544		      NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,
545		      NA, 47, NA, 0x5838, SOUTHWEST),
546	GPIO_PAD_CONF("SW90: PCIE_CLKREQ0B", NATIVE, M1, NA, NA, NA,
547		      NA, NA, NA, NA, NA, NA, NA, NA,
548		      NA, 48, NA, 0x5c00, SOUTHWEST),
549	GPIO_PAD_CONF("SW91: PCIE_CLKREQ1B", NATIVE, M1, NA, NA, NA,
550		      NA, NA, NA, NA, NA, NA, NA, NA,
551		      NA, 49, NA, 0x5c08, SOUTHWEST),
552	GPIO_PAD_CONF("SW93: PCIE_CLKREQ2B", NATIVE, M1, NA, NA, NA,
553		      NA, NA, NA, NA, NA, NA, NA, NA,
554		      NA, 51, NA, 0x5c18, SOUTHWEST),
555	GPIO_PAD_CONF("SW95: PCIE_CLKREQ3B", NATIVE, M2, NA, NA, NA,
556		      NA, NA, NA, NA, NA, NA, NA, NA,
557		      NA, 53, NA, 0x5c28, SOUTHWEST),
558	GPIO_PAD_CONF("SW75: SATA_GP0", GPIO, M1, GPO, HIGH, NA, NA,
559		      NA, NA, NA, NA, NA, NA, NA,
560		      NA, 40, NA, 0x5800, SOUTHWEST),
561	GPIO_PAD_CONF("SW76: SATA_GP1", GPIO, M1, GPI, HIGH, NA, NA,
562		      NA, NA, NA, NA, NA, NA, NA,
563		      NA, 41, NA, 0x5808, SOUTHWEST),
564	GPIO_PAD_CONF("SW78: SATA_GP2", NATIVE, M1, NA, NA, NA,
565		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
566		      NA, 43, NA, 0x5818, SOUTHWEST),
567	GPIO_PAD_CONF("SW80: SATA_GP3", GPIO, M2, GPI, LOW, NA,
568		      NA, NA, NA, NA, NA, NA, NA, NA,
569		      NA, 45, NA, 0x5828, SOUTHWEST),
570	GPIO_PAD_CONF("SW77: SATA_LEDN", NATIVE, M1, NA, NA, NA,
571		      NA, NA, NA, ENABLE, NA, NA, NA, NA,
572		      NA, 42, NA, 0x5810, SOUTHWEST),
573	GPIO_PAD_CONF("SW79: MF_SMB_ALERTB", NATIVE, M1, NA, NA,
574		      NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,
575		      NA, 44, NA, 0x5820, SOUTHWEST),
576	GPIO_PAD_CONF("SW81: MF_SMB_CLK", NATIVE, M1, NA, NA, NA,
577		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
578		      NA, 46, NA, 0x5830, SOUTHWEST),
579	GPIO_PAD_CONF("SW82: MF_SMB_DATA", NATIVE, M1, NA, NA, NA,
580		      NA, NA, P_20K_H, NA, NA, NA, NA, NA,
581		      NA, 47, NA, 0x5838, SOUTHWEST),
582
583	/* end of the table */
584	GPIO_PAD_CONF("GPIO PAD TABLE END", NATIVE, M1, NA, NA, NA,
585		      NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,
586		      NA, 0, NA, 0, TERMINATOR),
587};
588
589void update_fsp_gpio_configs(const struct gpio_family **family,
590			     const struct gpio_pad **pad)
591{
592	*family = gpio_family;
593	*pad = gpio_pad;
594}
595