Searched refs:M1 (Results 1 - 15 of 15) sorted by relevance

/u-boot/board/intel/cherryhill/
H A Dcherryhill.c19 GPIO_PAD_CONF("N37: CX_PRDY_B", NATIVE, M1, NA, NA, NA,
22 GPIO_PAD_CONF("N35: CX_PRDY_B_2", NATIVE, M1, NA, NA, NA,
25 GPIO_PAD_CONF("N39: CX_PREQ_B", NATIVE, M1, NA, NA, NA,
28 GPIO_PAD_CONF("N48: GP_CAMERASB00", GPIO, M1, GPO, LOW,
31 GPIO_PAD_CONF("N53: GP_CAMERASB01", GPIO, M1, GPO, LOW,
34 GPIO_PAD_CONF("N46: GP_CAMERASB02", GPIO, M1, GPO, LOW,
37 GPIO_PAD_CONF("N51: GP_CAMERASB03", GPIO, M1, GPO, LOW,
40 GPIO_PAD_CONF("N56: GP_CAMERASB04", GPIO, M1, GPO, LOW,
43 GPIO_PAD_CONF("N45: GP_CAMERASB05", GPIO, M1, GPO, LOW,
46 GPIO_PAD_CONF("N49: GP_CAMERASB06", GPIO, M1, GP
[all...]
/u-boot/board/ti/panda/
H A Dpanda_mux_data.h17 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
18 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
19 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
20 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
21 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
22 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
23 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
24 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
25 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
26 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cm
[all...]
/u-boot/board/ti/sdp4430/
H A Dsdp4430_mux_data.h16 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */
17 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */
18 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */
19 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */
20 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */
21 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */
22 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */
23 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */
24 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */
25 {GPMC_NWE, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_cm
[all...]
/u-boot/board/ti/dra7xx/
H A Dmux_data.h43 {GPMC_A13, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a13.qspi1_rtclk */
44 {GPMC_A14, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a14.qspi1_d3 */
45 {GPMC_A15, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a15.qspi1_d2 */
46 {GPMC_A16, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a16.qspi1_d0 */
47 {GPMC_A17, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a17.qspi1_d1 */
48 {GPMC_A18, (M1 | PIN_INPUT_PULLDOWN | MANUAL_MODE)}, /* gpmc_a18.qspi1_sclk */
49 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
50 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
51 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
52 {GPMC_A22, (M1 | PIN_INPUT_PULLU
[all...]
/u-boot/board/ti/am57xx/
H A Dmux_data.h50 {GPMC_A19, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a19.mmc2_dat4 */
51 {GPMC_A20, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a20.mmc2_dat5 */
52 {GPMC_A21, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a21.mmc2_dat6 */
53 {GPMC_A22, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a22.mmc2_dat7 */
54 {GPMC_A23, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a23.mmc2_clk */
55 {GPMC_A24, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a24.mmc2_dat0 */
56 {GPMC_A25, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a25.mmc2_dat1 */
57 {GPMC_A26, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a26.mmc2_dat2 */
58 {GPMC_A27, (M1 | PIN_INPUT_PULLUP)}, /* gpmc_a27.mmc2_dat3 */
59 {GPMC_CS1, (M1 | PIN_INPUT_PULLU
[all...]
/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dtie-asm.h83 rsr \at1, M1 // MAC16 option
148 wsr \at1, M1 // MAC16 option
/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dtie-asm.h76 rsr.M1 \at1 // MAC16 option
131 wsr.M1 \at1 // MAC16 option
/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dtie-asm.h47 rsr \at2, M1
90 wsr \at2, M1
/u-boot/board/beagle/beagle/
H A Dbeagle.h110 MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
111 MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\
205 MUX_VAL(CP(MCBSP3_DX), (IEN | PTD | DIS | M1)) /*UART2_CTS*/\
206 MUX_VAL(CP(MCBSP3_DR), (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
207 MUX_VAL(CP(MCBSP3_CLKX), (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
208 MUX_VAL(CP(MCBSP3_FSX), (IEN | PTD | DIS | M1)) /*UART2_RX*/\
218 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
219 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
220 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
221 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*SSI1_WAK
[all...]
/u-boot/arch/x86/include/asm/arch-braswell/
H A Dgpio.h15 M1, enumerator in enum:mode_list
/u-boot/board/lg/sniper/
H A Dsniper.h102 MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M1)) /* dsi_dx0 */ \
103 MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M1)) /* dsi_dy0 */ \
104 MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M1)) /* dsi_dx1 */ \
105 MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M1)) /* dsi_dy1 */ \
106 MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M1)) /* dsi_dx2 */ \
107 MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M1)) /* dsi_dy2 */ \
/u-boot/board/timll/devkit8000/
H A Ddevkit8000.h210 MUX_VAL(CP(MCBSP4_CLKX), (IEN | PTD | DIS | M1)) /*GPIO_152*/\
211 MUX_VAL(CP(MCBSP4_DR), (IEN | PTD | DIS | M1)) /*GPIO_153*/\
212 MUX_VAL(CP(MCBSP4_DX), (IEN | PTD | DIS | M1)) /*GPIO_154*/\
213 MUX_VAL(CP(MCBSP4_FSX), (IEN | PTD | DIS | M1)) /*GPIO_155*/\
/u-boot/arch/arm/include/asm/arch-omap4/
H A Dmux_omap4.h48 #define M1 1 macro
/u-boot/arch/arm/include/asm/arch-omap3/
H A Dmux.h42 #define M1 1 macro
/u-boot/arch/arm/include/asm/arch-omap5/
H A Dmux_dra7xx.h30 #define M1 1 macro

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