Searched refs:IP1_7_4 (Results 1 - 8 of 8) sorted by relevance

/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c59 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
174 #define IP1_7_4 FM(DU_DG5) F_(0, 0) F_(0, 0) FM(A9) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
271 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
432 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
433 PINMUX_IPSR_GPSR(IP1_7_4, A9),
434 PINMUX_IPSR_MSEL(IP1_7_4, FSO_CFE_1_N_A, SEL_RFSO_0),
2250 IP1_7_4
H A Dpfc-r8a77980.c61 #define GPSR0_9 F_(DU_DG5, IP1_7_4)
208 #define IP1_7_4 FM(DU_DG5) FM(SDA5) FM(GETHER_MDC_B) FM(A9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
321 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
506 PINMUX_IPSR_GPSR(IP1_7_4, DU_DG5),
507 PINMUX_IPSR_GPSR(IP1_7_4, SDA5),
508 PINMUX_IPSR_MSEL(IP1_7_4, GETHER_MDC_B, SEL_GETHER_1),
509 PINMUX_IPSR_GPSR(IP1_7_4, A9),
2704 IP1_7_4
H A Dpfc-r8a77995.c87 #define GPSR1_2 F_(DU_DB2, IP1_7_4)
220 #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
362 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
570 PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2),
571 PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2),
572 PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1),
2691 IP1_7_4
H A Dpfc-r8a77990.c131 #define GPSR2_10 F_(QSPI1_IO3, IP1_7_4)
226 #define IP1_7_4 FM(QSPI1_IO3) FM(RIF3_CLK_A) FM(HRX3_C) FM(VI4_DATA4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
390 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
594 PINMUX_IPSR_GPSR(IP1_7_4, QSPI1_IO3),
595 PINMUX_IPSR_MSEL(IP1_7_4, RIF3_CLK_A, SEL_DRIF3_0),
596 PINMUX_IPSR_MSEL(IP1_7_4, HRX3_C, SEL_HSCIF3_2),
597 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA4_A, SEL_VIN4_0),
4808 IP1_7_4
H A Dpfc-r8a77965.c148 #define GPSR2_3 F_(IRQ3, IP1_7_4)
270 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
453 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
705 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
706 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
707 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
708 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
709 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
710 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_
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H A Dpfc-r8a77951.c142 #define GPSR2_3 F_(IRQ3, IP1_7_4)
264 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
447 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
698 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
699 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
700 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
701 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
702 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
703 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_
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H A Dpfc-r8a7796.c148 #define GPSR2_3 F_(IRQ3, IP1_7_4)
270 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) F_(0, 0) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) FM(MSIOF3_SCK_E) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) macro
453 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
704 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
705 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
706 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
707 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
708 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
709 PINMUX_IPSR_MSEL(IP1_7_4, MSIOF3_SCK_
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H A Dpfc-r8a7790.c867 PINMUX_IPSR_GPSR(IP1_7_4, D10),
868 PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
869 PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
870 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
871 PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
872 PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
5187 /* IP1_7_4 [4] */

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