/u-boot/board/ti/panda/ |
H A D | panda_mux_data.h | 17 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ 18 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ 19 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ 20 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ 21 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ 22 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ 23 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ 24 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ 25 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ 26 {GPMC_NWE, (PTU | IEN | OFF_E [all...] |
H A D | panda.c | 91 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); 92 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); 103 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 105 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 107 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 121 writew((IEN | M3), (*ctrl)->control_padconf_core_base + 156 writew((IEN | M3),
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/u-boot/board/logicpd/omap3som/ |
H A D | omap3logic.h | 30 * IEN - Input Enable 48 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/ 49 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/ 50 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/ 51 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/ 52 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/ 53 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/ 54 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/ 55 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/ 56 MUX_VAL(CP(SDRC_D8), (IEN | PT [all...] |
/u-boot/board/ti/sdp4430/ |
H A D | sdp4430_mux_data.h | 16 {GPMC_AD0, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat0 */ 17 {GPMC_AD1, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat1 */ 18 {GPMC_AD2, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat2 */ 19 {GPMC_AD3, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat3 */ 20 {GPMC_AD4, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat4 */ 21 {GPMC_AD5, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat5 */ 22 {GPMC_AD6, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat6 */ 23 {GPMC_AD7, (PTU | IEN | OFF_EN | OFF_PD | OFF_IN | M1)}, /* sdmmc2_dat7 */ 24 {GPMC_NOE, (PTU | IEN | OFF_EN | OFF_OUT_PTD | M1)}, /* sdmmc2_clk */ 25 {GPMC_NWE, (PTU | IEN | OFF_E [all...] |
/u-boot/board/lg/sniper/ |
H A D | sniper.h | 15 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* sdrc_d0 */\ 16 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* sdrc_d1 */\ 17 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* sdrc_d2 */\ 18 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* sdrc_d3 */\ 19 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* sdrc_d4 */\ 20 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* sdrc_d5 */\ 21 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* sdrc_d6 */\ 22 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* sdrc_d7 */\ 23 MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /* sdrc_d8 */\ 24 MUX_VAL(CP(SDRC_D9), (IEN | PT [all...] |
/u-boot/board/logicpd/am3517evm/ |
H A D | am3517evm.h | 23 * IEN - Input Enable 34 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) \ 35 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) \ 36 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) \ 37 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) \ 38 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) \ 39 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) \ 40 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) \ 41 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) \ 42 MUX_VAL(CP(SDRC_D8), (IEN | PT [all...] |
/u-boot/board/ti/omap3evm/ |
H A D | evm.h | 39 * IEN - Input Enable 50 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 51 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 52 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 53 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 54 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 55 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 56 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 57 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 58 MUX_VAL(CP(SDRC_D8), (IEN | PT [all...] |
/u-boot/board/isee/igep00x0/ |
H A D | igep00x0.h | 10 * IEN - Input Enable 20 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /* SDRC_D0 */\ 21 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /* SDRC_D1 */\ 22 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /* SDRC_D2 */\ 23 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /* SDRC_D3 */\ 24 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /* SDRC_D4 */\ 25 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /* SDRC_D5 */\ 26 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /* SDRC_D6 */\ 27 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /* SDRC_D7 */\ 28 MUX_VAL(CP(SDRC_D8), (IEN | PT [all...] |
/u-boot/board/timll/devkit8000/ |
H A D | devkit8000.h | 22 * IEN - Input Enable 34 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 35 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 36 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 37 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 38 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 39 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 40 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 41 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 42 MUX_VAL(CP(SDRC_D8), (IEN | PT [all...] |
/u-boot/board/beagle/beagle/ |
H A D | beagle.h | 29 * IEN - Input Enable 40 MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ 41 MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ 42 MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ 43 MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ 44 MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ 45 MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ 46 MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ 47 MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ 48 MUX_VAL(CP(SDRC_D8), (IEN | PT [all...] |
/u-boot/include/renesas/ |
H A D | rzg2l-pfc.h | 49 * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits 77 #define IEN(n) (0x1800 + (n) * 8) macro
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/u-boot/arch/arm/include/asm/arch-omap4/ |
H A D | mux_omap4.h | 40 #define IEN (1 << 8) macro
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/u-boot/arch/arm/include/asm/arch-omap3/ |
H A D | mux.h | 11 * IEN - Input Enable 26 #define IEN (1 << 8) macro
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/u-boot/drivers/pinctrl/renesas/ |
H A D | rzg2l-pfc.c | 386 dev_err(dev, "pin does not support IEN\n"); 390 dev_dbg(dev, "port off %u:%u set IEN=%u\n", 392 rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument);
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