1// SPDX-License-Identifier: GPL-2.0 2/* 3 * RZ/G2L Pin Function Controller 4 * 5 * Copyright (C) 2021-2023 Renesas Electronics Corp. 6 */ 7 8#include <asm/io.h> 9#include <clk.h> 10#include <dm.h> 11#include <dm/device-internal.h> 12#include <dm/device.h> 13#include <dm/device_compat.h> 14#include <dm/devres.h> 15#include <dm/lists.h> 16#include <dm/pinctrl.h> 17#include <renesas/rzg2l-pfc.h> 18#include <reset.h> 19 20struct rzg2l_pfc_driver_data { 21 uint num_dedicated_pins; 22 uint num_ports; 23 const u32 *gpio_configs; 24}; 25 26struct rzg2l_dedicated_configs { 27 const char *name; 28 u32 config; 29}; 30 31/* 32 * We need to ensure that the module clock is enabled and all resets are 33 * de-asserted before using either the gpio or pinctrl functionality. Error 34 * handling can be quite simple here as if the PFC cannot be enabled then we 35 * will not be able to progress with the boot anyway. 36 */ 37int rzg2l_pfc_enable(struct udevice *dev) 38{ 39 struct reset_ctl_bulk rsts; 40 struct clk clk; 41 int ret; 42 43 ret = clk_get_by_index(dev, 0, &clk); 44 if (ret < 0) { 45 dev_err(dev, "failed to get gpio module clock\n"); 46 return ret; 47 } 48 49 ret = clk_enable(&clk); 50 if (ret < 0) { 51 dev_err(dev, "failed to enable gpio module clock\n"); 52 return ret; 53 } 54 55 ret = reset_get_bulk(dev, &rsts); 56 if (ret < 0) { 57 dev_err(dev, "failed to get reset lines\n"); 58 return ret; 59 } 60 61 ret = reset_deassert_bulk(&rsts); 62 if (ret < 0) { 63 dev_err(dev, "failed to de-assert reset lines\n"); 64 return ret; 65 } 66 67 return 0; 68} 69 70bool rzg2l_port_validate(const struct rzg2l_pfc_data *data, u32 port, u8 pin) 71{ 72 return (port < data->num_ports) && 73 (pin < RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[port])); 74} 75 76/* Decode a pin selector, returning the port index and setting *pin to the pin 77 * index. Returns -1 on error, which can be checked directly or by calling 78 * rzg2l_port_validate(). 79 */ 80static int rzg2l_selector_decode(const struct rzg2l_pfc_data *data, 81 unsigned int selector, 82 u8 *pin) 83{ 84 int port; 85 86 selector -= data->num_dedicated_pins; 87 for (port = 0; port < data->num_ports; port++) { 88 u8 num_pins = RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[port]); 89 if (selector < num_pins) { 90 *pin = (u8)selector; 91 return port; 92 } 93 selector -= num_pins; 94 } 95 return -EINVAL; 96} 97 98static unsigned int rzg2l_selector_encode(const struct rzg2l_pfc_data *data, 99 u32 port, u8 pin) 100{ 101 unsigned int selector = data->num_dedicated_pins + pin; 102 u32 i; 103 104 for (i = 0; i < port; i++) 105 selector += RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[i]); 106 107 return selector; 108} 109 110static const char * const rzg2l_gpio_names[] = { 111 "P0_0", "P0_1", "P0_2", "P0_3", "P0_4", "P0_5", "P0_6", "P0_7", 112 "P1_0", "P1_1", "P1_2", "P1_3", "P1_4", "P1_5", "P1_6", "P1_7", 113 "P2_0", "P2_1", "P2_2", "P2_3", "P2_4", "P2_5", "P2_6", "P2_7", 114 "P3_0", "P3_1", "P3_2", "P3_3", "P3_4", "P3_5", "P3_6", "P3_7", 115 "P4_0", "P4_1", "P4_2", "P4_3", "P4_4", "P4_5", "P4_6", "P4_7", 116 "P5_0", "P5_1", "P5_2", "P5_3", "P5_4", "P5_5", "P5_6", "P5_7", 117 "P6_0", "P6_1", "P6_2", "P6_3", "P6_4", "P6_5", "P6_6", "P6_7", 118 "P7_0", "P7_1", "P7_2", "P7_3", "P7_4", "P7_5", "P7_6", "P7_7", 119 "P8_0", "P8_1", "P8_2", "P8_3", "P8_4", "P8_5", "P8_6", "P8_7", 120 "P9_0", "P9_1", "P9_2", "P9_3", "P9_4", "P9_5", "P9_6", "P9_7", 121 "P10_0", "P10_1", "P10_2", "P10_3", "P10_4", "P10_5", "P10_6", "P10_7", 122 "P11_0", "P11_1", "P11_2", "P11_3", "P11_4", "P11_5", "P11_6", "P11_7", 123 "P12_0", "P12_1", "P12_2", "P12_3", "P12_4", "P12_5", "P12_6", "P12_7", 124 "P13_0", "P13_1", "P13_2", "P13_3", "P13_4", "P13_5", "P13_6", "P13_7", 125 "P14_0", "P14_1", "P14_2", "P14_3", "P14_4", "P14_5", "P14_6", "P14_7", 126 "P15_0", "P15_1", "P15_2", "P15_3", "P15_4", "P15_5", "P15_6", "P15_7", 127 "P16_0", "P16_1", "P16_2", "P16_3", "P16_4", "P16_5", "P16_6", "P16_7", 128 "P17_0", "P17_1", "P17_2", "P17_3", "P17_4", "P17_5", "P17_6", "P17_7", 129 "P18_0", "P18_1", "P18_2", "P18_3", "P18_4", "P18_5", "P18_6", "P18_7", 130 "P19_0", "P19_1", "P19_2", "P19_3", "P19_4", "P19_5", "P19_6", "P19_7", 131 "P20_0", "P20_1", "P20_2", "P20_3", "P20_4", "P20_5", "P20_6", "P20_7", 132 "P21_0", "P21_1", "P21_2", "P21_3", "P21_4", "P21_5", "P21_6", "P21_7", 133 "P22_0", "P22_1", "P22_2", "P22_3", "P22_4", "P22_5", "P22_6", "P22_7", 134 "P23_0", "P23_1", "P23_2", "P23_3", "P23_4", "P23_5", "P23_6", "P23_7", 135 "P24_0", "P24_1", "P24_2", "P24_3", "P24_4", "P24_5", "P24_6", "P24_7", 136 "P25_0", "P25_1", "P25_2", "P25_3", "P25_4", "P25_5", "P25_6", "P25_7", 137 "P26_0", "P26_1", "P26_2", "P26_3", "P26_4", "P26_5", "P26_6", "P26_7", 138 "P27_0", "P27_1", "P27_2", "P27_3", "P27_4", "P27_5", "P27_6", "P27_7", 139 "P28_0", "P28_1", "P28_2", "P28_3", "P28_4", "P28_5", "P28_6", "P28_7", 140 "P29_0", "P29_1", "P29_2", "P29_3", "P29_4", "P29_5", "P29_6", "P29_7", 141 "P30_0", "P30_1", "P30_2", "P30_3", "P30_4", "P30_5", "P30_6", "P30_7", 142 "P31_0", "P31_1", "P31_2", "P31_3", "P31_4", "P31_5", "P31_6", "P31_7", 143 "P32_0", "P32_1", "P32_2", "P32_3", "P32_4", "P32_5", "P32_6", "P32_7", 144 "P33_0", "P33_1", "P33_2", "P33_3", "P33_4", "P33_5", "P33_6", "P33_7", 145 "P34_0", "P34_1", "P34_2", "P34_3", "P34_4", "P34_5", "P34_6", "P34_7", 146 "P35_0", "P35_1", "P35_2", "P35_3", "P35_4", "P35_5", "P35_6", "P35_7", 147 "P36_0", "P36_1", "P36_2", "P36_3", "P36_4", "P36_5", "P36_6", "P36_7", 148 "P37_0", "P37_1", "P37_2", "P37_3", "P37_4", "P37_5", "P37_6", "P37_7", 149 "P38_0", "P38_1", "P38_2", "P38_3", "P38_4", "P38_5", "P38_6", "P38_7", 150 "P39_0", "P39_1", "P39_2", "P39_3", "P39_4", "P39_5", "P39_6", "P39_7", 151 "P40_0", "P40_1", "P40_2", "P40_3", "P40_4", "P40_5", "P40_6", "P40_7", 152 "P41_0", "P41_1", "P41_2", "P41_3", "P41_4", "P41_5", "P41_6", "P41_7", 153 "P42_0", "P42_1", "P42_2", "P42_3", "P42_4", "P42_5", "P42_6", "P42_7", 154 "P43_0", "P43_1", "P43_2", "P43_3", "P43_4", "P43_5", "P43_6", "P43_7", 155 "P44_0", "P44_1", "P44_2", "P44_3", "P44_4", "P44_5", "P44_6", "P44_7", 156 "P45_0", "P45_1", "P45_2", "P45_3", "P45_4", "P45_5", "P45_6", "P45_7", 157 "P46_0", "P46_1", "P46_2", "P46_3", "P46_4", "P46_5", "P46_6", "P46_7", 158 "P47_0", "P47_1", "P47_2", "P47_3", "P47_4", "P47_5", "P47_6", "P47_7", 159 "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", 160}; 161 162static const u32 r9a07g044_gpio_configs[] = { 163 RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), 164 RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), 165 RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), 166 RZG2L_GPIO_PORT_PACK(2, 0x13, RZG2L_MPXED_PIN_FUNCS), 167 RZG2L_GPIO_PORT_PACK(2, 0x14, RZG2L_MPXED_PIN_FUNCS), 168 RZG2L_GPIO_PORT_PACK(3, 0x15, RZG2L_MPXED_PIN_FUNCS), 169 RZG2L_GPIO_PORT_PACK(2, 0x16, RZG2L_MPXED_PIN_FUNCS), 170 RZG2L_GPIO_PORT_PACK(3, 0x17, RZG2L_MPXED_PIN_FUNCS), 171 RZG2L_GPIO_PORT_PACK(3, 0x18, RZG2L_MPXED_PIN_FUNCS), 172 RZG2L_GPIO_PORT_PACK(2, 0x19, RZG2L_MPXED_PIN_FUNCS), 173 RZG2L_GPIO_PORT_PACK(2, 0x1a, RZG2L_MPXED_PIN_FUNCS), 174 RZG2L_GPIO_PORT_PACK(2, 0x1b, RZG2L_MPXED_PIN_FUNCS), 175 RZG2L_GPIO_PORT_PACK(2, 0x1c, RZG2L_MPXED_PIN_FUNCS), 176 RZG2L_GPIO_PORT_PACK(3, 0x1d, RZG2L_MPXED_PIN_FUNCS), 177 RZG2L_GPIO_PORT_PACK(2, 0x1e, RZG2L_MPXED_PIN_FUNCS), 178 RZG2L_GPIO_PORT_PACK(2, 0x1f, RZG2L_MPXED_PIN_FUNCS), 179 RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), 180 RZG2L_GPIO_PORT_PACK(3, 0x21, RZG2L_MPXED_PIN_FUNCS), 181 RZG2L_GPIO_PORT_PACK(2, 0x22, RZG2L_MPXED_PIN_FUNCS), 182 RZG2L_GPIO_PORT_PACK(2, 0x23, RZG2L_MPXED_PIN_FUNCS), 183 RZG2L_GPIO_PORT_PACK(3, 0x24, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 184 RZG2L_GPIO_PORT_PACK(2, 0x25, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 185 RZG2L_GPIO_PORT_PACK(2, 0x26, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 186 RZG2L_GPIO_PORT_PACK(2, 0x27, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 187 RZG2L_GPIO_PORT_PACK(2, 0x28, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 188 RZG2L_GPIO_PORT_PACK(2, 0x29, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 189 RZG2L_GPIO_PORT_PACK(2, 0x2a, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 190 RZG2L_GPIO_PORT_PACK(2, 0x2b, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 191 RZG2L_GPIO_PORT_PACK(2, 0x2c, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), 192 RZG2L_GPIO_PORT_PACK(2, 0x2d, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 193 RZG2L_GPIO_PORT_PACK(2, 0x2e, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 194 RZG2L_GPIO_PORT_PACK(2, 0x2f, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 195 RZG2L_GPIO_PORT_PACK(2, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 196 RZG2L_GPIO_PORT_PACK(2, 0x31, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 197 RZG2L_GPIO_PORT_PACK(2, 0x32, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 198 RZG2L_GPIO_PORT_PACK(2, 0x33, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 199 RZG2L_GPIO_PORT_PACK(2, 0x34, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 200 RZG2L_GPIO_PORT_PACK(3, 0x35, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH1)), 201 RZG2L_GPIO_PORT_PACK(2, 0x36, RZG2L_MPXED_PIN_FUNCS), 202 RZG2L_GPIO_PORT_PACK(3, 0x37, RZG2L_MPXED_PIN_FUNCS), 203 RZG2L_GPIO_PORT_PACK(3, 0x38, RZG2L_MPXED_PIN_FUNCS), 204 RZG2L_GPIO_PORT_PACK(2, 0x39, RZG2L_MPXED_PIN_FUNCS), 205 RZG2L_GPIO_PORT_PACK(5, 0x3a, RZG2L_MPXED_PIN_FUNCS), 206 RZG2L_GPIO_PORT_PACK(4, 0x3b, RZG2L_MPXED_PIN_FUNCS), 207 RZG2L_GPIO_PORT_PACK(4, 0x3c, RZG2L_MPXED_PIN_FUNCS), 208 RZG2L_GPIO_PORT_PACK(4, 0x3d, RZG2L_MPXED_PIN_FUNCS), 209 RZG2L_GPIO_PORT_PACK(4, 0x3e, RZG2L_MPXED_PIN_FUNCS), 210 RZG2L_GPIO_PORT_PACK(4, 0x3f, RZG2L_MPXED_PIN_FUNCS), 211 RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), 212}; 213 214static const struct { 215 struct rzg2l_dedicated_configs common[35]; 216 struct rzg2l_dedicated_configs rzg2l_pins[7]; 217} rzg2l_dedicated_pins = { 218 .common = { 219 { "NMI", RZG2L_SINGLE_PIN_PACK(0x1, 0, 220 (PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL)) }, 221 { "TMS/SWDIO", RZG2L_SINGLE_PIN_PACK(0x2, 0, 222 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 223 { "TDO", RZG2L_SINGLE_PIN_PACK(0x3, 0, 224 (PIN_CFG_IOLH_A | PIN_CFG_SR | PIN_CFG_IEN)) }, 225 { "AUDIO_CLK1", RZG2L_SINGLE_PIN_PACK(0x4, 0, PIN_CFG_IEN) }, 226 { "AUDIO_CLK2", RZG2L_SINGLE_PIN_PACK(0x4, 1, PIN_CFG_IEN) }, 227 { "SD0_CLK", RZG2L_SINGLE_PIN_PACK(0x6, 0, 228 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 229 { "SD0_CMD", RZG2L_SINGLE_PIN_PACK(0x6, 1, 230 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 231 { "SD0_RST#", RZG2L_SINGLE_PIN_PACK(0x6, 2, 232 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD0)) }, 233 { "SD0_DATA0", RZG2L_SINGLE_PIN_PACK(0x7, 0, 234 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 235 { "SD0_DATA1", RZG2L_SINGLE_PIN_PACK(0x7, 1, 236 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 237 { "SD0_DATA2", RZG2L_SINGLE_PIN_PACK(0x7, 2, 238 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 239 { "SD0_DATA3", RZG2L_SINGLE_PIN_PACK(0x7, 3, 240 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 241 { "SD0_DATA4", RZG2L_SINGLE_PIN_PACK(0x7, 4, 242 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 243 { "SD0_DATA5", RZG2L_SINGLE_PIN_PACK(0x7, 5, 244 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 245 { "SD0_DATA6", RZG2L_SINGLE_PIN_PACK(0x7, 6, 246 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 247 { "SD0_DATA7", RZG2L_SINGLE_PIN_PACK(0x7, 7, 248 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD0)) }, 249 { "SD1_CLK", RZG2L_SINGLE_PIN_PACK(0x8, 0, 250 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_SD1)) }, 251 { "SD1_CMD", RZG2L_SINGLE_PIN_PACK(0x8, 1, 252 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 253 { "SD1_DATA0", RZG2L_SINGLE_PIN_PACK(0x9, 0, 254 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 255 { "SD1_DATA1", RZG2L_SINGLE_PIN_PACK(0x9, 1, 256 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 257 { "SD1_DATA2", RZG2L_SINGLE_PIN_PACK(0x9, 2, 258 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 259 { "SD1_DATA3", RZG2L_SINGLE_PIN_PACK(0x9, 3, 260 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IEN | PIN_CFG_IO_VMC_SD1)) }, 261 { "QSPI0_SPCLK", RZG2L_SINGLE_PIN_PACK(0xa, 0, 262 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 263 { "QSPI0_IO0", RZG2L_SINGLE_PIN_PACK(0xa, 1, 264 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 265 { "QSPI0_IO1", RZG2L_SINGLE_PIN_PACK(0xa, 2, 266 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 267 { "QSPI0_IO2", RZG2L_SINGLE_PIN_PACK(0xa, 3, 268 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 269 { "QSPI0_IO3", RZG2L_SINGLE_PIN_PACK(0xa, 4, 270 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 271 { "QSPI0_SSL", RZG2L_SINGLE_PIN_PACK(0xa, 5, 272 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 273 { "QSPI_RESET#", RZG2L_SINGLE_PIN_PACK(0xc, 0, 274 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 275 { "QSPI_WP#", RZG2L_SINGLE_PIN_PACK(0xc, 1, 276 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 277 { "WDTOVF_PERROUT#", RZG2L_SINGLE_PIN_PACK(0xd, 0, (PIN_CFG_IOLH_A | PIN_CFG_SR)) }, 278 { "RIIC0_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 0, PIN_CFG_IEN) }, 279 { "RIIC0_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 1, PIN_CFG_IEN) }, 280 { "RIIC1_SDA", RZG2L_SINGLE_PIN_PACK(0xe, 2, PIN_CFG_IEN) }, 281 { "RIIC1_SCL", RZG2L_SINGLE_PIN_PACK(0xe, 3, PIN_CFG_IEN) }, 282 }, 283 .rzg2l_pins = { 284 { "QSPI_INT#", RZG2L_SINGLE_PIN_PACK(0xc, 2, (PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 285 { "QSPI1_SPCLK", RZG2L_SINGLE_PIN_PACK(0xb, 0, 286 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 287 { "QSPI1_IO0", RZG2L_SINGLE_PIN_PACK(0xb, 1, 288 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 289 { "QSPI1_IO1", RZG2L_SINGLE_PIN_PACK(0xb, 2, 290 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 291 { "QSPI1_IO2", RZG2L_SINGLE_PIN_PACK(0xb, 3, 292 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 293 { "QSPI1_IO3", RZG2L_SINGLE_PIN_PACK(0xb, 4, 294 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 295 { "QSPI1_SSL", RZG2L_SINGLE_PIN_PACK(0xb, 5, 296 (PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_IO_VMC_QSPI)) }, 297 } 298}; 299 300static void rzg2l_rmw_pin_config(const struct rzg2l_pfc_data *data, u32 offset, 301 u8 pin, u32 mask, u32 val) 302{ 303 void __iomem *addr = data->base + offset; 304 305 /* handle _L/_H for 32-bit register read/write */ 306 if (pin >= 4) { 307 pin -= 4; 308 addr += 4; 309 } 310 311 clrsetbits_le32(addr, mask << (pin * 8), val << (pin * 8)); 312} 313 314static int rzg2l_get_pins_count(struct udevice *dev) 315{ 316 const struct rzg2l_pfc_data *data = 317 (const struct rzg2l_pfc_data *)dev_get_driver_data(dev); 318 319 return data->num_dedicated_pins + data->num_pins; 320} 321 322static const char *rzg2l_get_pin_name(struct udevice *dev, unsigned int selector) 323{ 324 const struct rzg2l_pfc_data *data = 325 (const struct rzg2l_pfc_data *)dev_get_driver_data(dev); 326 int port; 327 u8 pin; 328 329 if (selector < data->num_dedicated_pins) { 330 if (selector >= ARRAY_SIZE(rzg2l_dedicated_pins.common)) { 331 unsigned int u = selector - ARRAY_SIZE(rzg2l_dedicated_pins.common); 332 return rzg2l_dedicated_pins.rzg2l_pins[u].name; 333 } else { 334 return rzg2l_dedicated_pins.common[selector].name; 335 } 336 } 337 338 port = rzg2l_selector_decode(data, selector, &pin); 339 if (port < 0) 340 return "(invalid pin)"; 341 return rzg2l_gpio_names[pin + 8 * port]; 342} 343 344static int rzg2l_pinconf_set(struct udevice *dev, unsigned int pin_selector, 345 unsigned int param, unsigned int argument) 346{ 347 const struct rzg2l_pfc_data *data = 348 (const struct rzg2l_pfc_data *)dev_get_driver_data(dev); 349 u32 cfg, port_offset; 350 u8 pin; 351 352 if (pin_selector >= data->num_dedicated_pins) { 353 /* The pin selector refers to a multiplexed pin */ 354 int port = rzg2l_selector_decode(data, pin_selector, &pin); 355 if (port < 0) { 356 dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); 357 return port; 358 } 359 360 cfg = data->gpio_configs[port]; 361 port_offset = P(port); 362 } else { 363 /* The pin selector refers to a dedicated function pin */ 364 const struct rzg2l_dedicated_configs *dedicated_config; 365 366 if (pin_selector >= data->num_dedicated_pins) { 367 dev_err(dev, "Invalid dedicated pin %u\n", pin_selector); 368 return -EINVAL; 369 } 370 371 if (pin_selector >= ARRAY_SIZE(rzg2l_dedicated_pins.common)) { 372 pin_selector -= ARRAY_SIZE(rzg2l_dedicated_pins.common); 373 dedicated_config = &rzg2l_dedicated_pins.rzg2l_pins[pin_selector]; 374 } else { 375 dedicated_config = &rzg2l_dedicated_pins.common[pin_selector]; 376 } 377 378 port_offset = RZG2L_SINGLE_PIN_GET_PORT_OFFSET(dedicated_config->config); 379 pin = RZG2L_SINGLE_PIN_GET_BIT(dedicated_config->config); 380 cfg = RZG2L_SINGLE_PIN_GET_CFGS(dedicated_config->config); 381 } 382 383 switch (param) { 384 case PIN_CONFIG_INPUT_ENABLE: { 385 if (!(cfg & PIN_CFG_IEN)) { 386 dev_err(dev, "pin does not support IEN\n"); 387 return -EINVAL; 388 } 389 390 dev_dbg(dev, "port off %u:%u set IEN=%u\n", 391 port_offset, pin, argument); 392 rzg2l_rmw_pin_config(data, IEN(port_offset), pin, IEN_MASK, !!argument); 393 break; 394 } 395 396 case PIN_CONFIG_POWER_SOURCE: { 397 u32 pwr_reg = 0x0; 398 399 /* argument is in mV */ 400 if (argument != 1800 && argument != 3300) { 401 dev_err(dev, "Invalid mV %u\n", argument); 402 return -EINVAL; 403 } 404 405 /* 406 * TODO: PIN_CFG_IO_VMC_ETH0 & PIN_CFG_IO_VMC_ETH1 will be 407 * handled when the RZ/G2L Ethernet driver is added. 408 */ 409 if (cfg & PIN_CFG_IO_VMC_SD0) { 410 dev_dbg(dev, "port off %u:%u set SD_CH 0 PVDD=%u\n", 411 port_offset, pin, argument); 412 pwr_reg = SD_CH(0); 413 } else if (cfg & PIN_CFG_IO_VMC_SD1) { 414 dev_dbg(dev, "port off %u:%u set SD_CH 1 PVDD=%u\n", 415 port_offset, pin, argument); 416 pwr_reg = SD_CH(1); 417 } else if (cfg & PIN_CFG_IO_VMC_QSPI) { 418 dev_dbg(dev, "port off %u:%u set QSPI PVDD=%u\n", 419 port_offset, pin, argument); 420 pwr_reg = QSPI; 421 } else { 422 dev_dbg(dev, "pin power source is not selectable\n"); 423 return -EINVAL; 424 } 425 426 writel((argument == 1800) ? PVDD_1800 : PVDD_3300, 427 data->base + pwr_reg); 428 break; 429 } 430 431 default: 432 dev_err(dev, "Invalid pinconf parameter\n"); 433 return -EOPNOTSUPP; 434 } 435 436 return 0; 437} 438 439static int rzg2l_pinmux_property_set(struct udevice *dev, u32 pinmux_group) 440{ 441 const struct rzg2l_pfc_data *data = 442 (const struct rzg2l_pfc_data *)dev_get_driver_data(dev); 443 u32 port, pin, func, pfc_state; 444 u8 pmc_state; 445 446 func = RZG2L_PINMUX_TO_FUNC(pinmux_group); 447 if (func > 5) { 448 dev_err(dev, "Invalid pin function %u\n", func); 449 return -EINVAL; 450 } 451 452 port = RZG2L_PINMUX_TO_PORT(pinmux_group); 453 pin = RZG2L_PINMUX_TO_PIN(pinmux_group); 454 if (!rzg2l_port_validate(data, port, pin)) { 455 dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); 456 return -EINVAL; 457 } 458 459 /* Check current PMC & PFC to decide if we need to change anything. */ 460 pmc_state = readb(data->base + PMC(port)) & BIT(pin); 461 pfc_state = (readl(data->base + PFC(port)) >> (pin * 4)) & PFC_MASK; 462 if (pmc_state && pfc_state == func) 463 return 0; 464 465 dev_dbg(dev, "pinmux port %u pin %u func %u\n", port, pin, func); 466 467 /* Set pin to 'Non-use (Hi-Z input protection)' */ 468 clrbits_le16(data->base + PM(port), PM_MASK << (pin * 2)); 469 470 /* Temporarily switch to GPIO mode with PMC register */ 471 clrbits_8(data->base + PMC(port), BIT(pin)); 472 473 /* Set the PWPR register to allow PFC register to write */ 474 writel(0x0, data->base + PWPR); /* B0WI=0, PFCWE=0 */ 475 writel(PWPR_PFCWE, data->base + PWPR); /* B0WI=0, PFCWE=1 */ 476 477 /* Select Pin function mode with PFC register */ 478 clrsetbits_le32(data->base + PFC(port), PFC_MASK << (pin * 4), 479 func << (pin * 4)); 480 481 /* Set the PWPR register to be write-protected */ 482 writel(0x0, data->base + PWPR); /* B0WI=0, PFCWE=0 */ 483 writel(PWPR_B0WI, data->base + PWPR); /* B0WI=1, PFCWE=0 */ 484 485 /* Switch to Peripheral pin function with PMC register */ 486 setbits_8(data->base + PMC(port), BIT(pin)); 487 488 return rzg2l_selector_encode(data, port, pin); 489} 490 491static int rzg2l_get_pin_muxing(struct udevice *dev, unsigned int selector, 492 char *buf, int size) 493{ 494 const struct rzg2l_pfc_data *data = 495 (const struct rzg2l_pfc_data *)dev_get_driver_data(dev); 496 u32 pmc_state; 497 int port; 498 u8 pin; 499 500 if (selector < data->num_dedicated_pins) { 501 snprintf(buf, size, rzg2l_get_pin_name(dev, selector)); 502 return 0; 503 } 504 505 port = rzg2l_selector_decode(data, selector, &pin); 506 if (port < 0) { 507 dev_err(dev, "Invalid pin selector %u:%u\n", port, pin); 508 return port; 509 } 510 511 pmc_state = readb(data->base + PMC(port)) & BIT(pin); 512 if (pmc_state) { 513 u32 pfc_state = (readl(data->base + PFC(port)) >> (pin * 4)) & PFC_MASK; 514 snprintf(buf, size, "Function %d", pfc_state); 515 return 0; 516 } 517 518 snprintf(buf, size, "GPIO"); 519 return 0; 520} 521 522static const struct pinconf_param rzg2l_pinconf_params[] = { 523 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 }, 524 { "power-source", PIN_CONFIG_POWER_SOURCE, 3300 /* mV */ }, 525}; 526 527static const struct pinctrl_ops rzg2l_pinctrl_ops = { 528 .get_pins_count = rzg2l_get_pins_count, 529 .get_pin_name = rzg2l_get_pin_name, 530 531 .pinconf_num_params = ARRAY_SIZE(rzg2l_pinconf_params), 532 .pinconf_params = rzg2l_pinconf_params, 533 .pinconf_set = rzg2l_pinconf_set, 534 535 .pinmux_property_set = rzg2l_pinmux_property_set, 536 .set_state = pinctrl_generic_set_state, 537 .get_pin_muxing = rzg2l_get_pin_muxing, 538}; 539 540static int rzg2l_pinctrl_probe(struct udevice *dev) 541{ 542 return rzg2l_pfc_enable(dev); 543} 544 545U_BOOT_DRIVER(rzg2l_pfc_pinctrl) = { 546 .name = "rzg2l-pfc-pinctrl", 547 .id = UCLASS_PINCTRL, 548 .ops = &rzg2l_pinctrl_ops, 549 .probe = rzg2l_pinctrl_probe, 550}; 551 552static const struct rzg2l_pfc_driver_data r9a07g044_driver_data = { 553 .num_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common) + 554 ARRAY_SIZE(rzg2l_dedicated_pins.rzg2l_pins), 555 .num_ports = ARRAY_SIZE(r9a07g044_gpio_configs), 556 .gpio_configs = r9a07g044_gpio_configs, 557}; 558 559static const struct udevice_id rzg2l_pfc_ids[] = { 560 { .compatible = "renesas,r9a07g044-pinctrl", .data = (ulong)&r9a07g044_driver_data }, 561 { /* sentinel */ } 562}; 563 564static int rzg2l_pfc_bind(struct udevice *parent) 565{ 566 struct rzg2l_pfc_driver_data *driver_data; 567 struct rzg2l_pfc_data *data; 568 struct udevice *pinctrl_dev; 569 struct driver *drv; 570 unsigned int i; 571 int ret; 572 573 driver_data = 574 (struct rzg2l_pfc_driver_data *)dev_get_driver_data(parent); 575 if (!driver_data) 576 return -EINVAL; 577 data = devm_kmalloc(parent, sizeof(*data), 0); 578 if (!data) 579 return -ENOMEM; 580 581 data->base = dev_read_addr_ptr(parent); 582 if (!data->base) 583 return -EINVAL; 584 data->num_dedicated_pins = driver_data->num_dedicated_pins; 585 data->num_ports = driver_data->num_ports; 586 data->gpio_configs = driver_data->gpio_configs; 587 588 data->num_pins = 0; 589 for (i = 0; i < data->num_ports; i++) 590 data->num_pins += RZG2L_GPIO_PORT_GET_PINCNT(data->gpio_configs[i]); 591 dev_dbg(parent, "%u dedicated pins, %u muxed ports, %u muxed pins\n", 592 data->num_dedicated_pins, data->num_ports, data->num_pins); 593 594 drv = lists_driver_lookup_name("rzg2l-pfc-pinctrl"); 595 if (!drv) 596 return -ENOENT; 597 598 ret = device_bind_with_driver_data(parent, drv, parent->name, 599 (ulong)data, dev_ofnode(parent), 600 &pinctrl_dev); 601 602 if (!ret && IS_ENABLED(CONFIG_RZG2L_GPIO)) { 603 drv = lists_driver_lookup_name("rzg2l-pfc-gpio"); 604 if (!drv) { 605 device_unbind(pinctrl_dev); 606 return -ENOENT; 607 } 608 609 ret = device_bind_with_driver_data(parent, drv, parent->name, 610 (ulong)data, 611 dev_ofnode(parent), NULL); 612 if (ret) 613 device_unbind(pinctrl_dev); 614 } 615 616 return ret; 617} 618 619U_BOOT_DRIVER(rzg2l_pfc) = { 620 .name = "rzg2l-pfc", 621 .id = UCLASS_NOP, 622 .of_match = rzg2l_pfc_ids, 623 .bind = rzg2l_pfc_bind, 624}; 625