Searched refs:DDR_CTL_BASE_ADDR (Results 1 - 2 of 2) sorted by relevance

/u-boot/drivers/ddr/imx/imx8ulp/
H A Dddr_init.c11 #define DENALI_CTL_00 (DDR_CTL_BASE_ADDR + 4 * 0)
14 #define DENALI_CTL_03 (DDR_CTL_BASE_ADDR + 4 * 3)
15 #define DENALI_CTL_197 (DDR_CTL_BASE_ADDR + 4 * 197)
16 #define DENALI_CTL_250 (DDR_CTL_BASE_ADDR + 4 * 250)
17 #define DENALI_CTL_251 (DDR_CTL_BASE_ADDR + 4 * 251)
18 #define DENALI_CTL_266 (DDR_CTL_BASE_ADDR + 4 * 266)
21 #define DENALI_CTL_614 (DDR_CTL_BASE_ADDR + 4 * 614)
22 #define DENALI_CTL_615 (DDR_CTL_BASE_ADDR + 4 * 615)
30 #define DENALI_CTL_23 (DDR_CTL_BASE_ADDR + 4 * 23)
31 #define DENALI_CTL_25 (DDR_CTL_BASE_ADDR
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/u-boot/arch/arm/include/asm/arch-imx8ulp/
H A Dimx-regs.h57 #define DDR_CTL_BASE_ADDR 0x2E060000 macro

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