Searched refs:CLK_INFRA_NR_CLK (Results 1 - 25 of 49) sorted by relevance

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/u-boot/arch/xtensa/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/arch/arm/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/arch/nios2/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/arch/sandbox/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/arch/x86/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/arch/mips/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/arch/microblaze/dts/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/include/dt-bindings/clock/
H A Dmt7986-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
154 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
155 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
156 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
157 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
158 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
159 #define CK_INFRA_PWM1_SEL (5 + CLK_INFRA_NR_CLK)
160 #define CK_INFRA_PWM2_SEL (6 + CLK_INFRA_NR_CLK)
161 #define CK_INFRA_PWM_BSEL (7 + CLK_INFRA_NR_CLK)
162 #define CK_INFRA_PCIE_SEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7981-clk.h50 #define CLK_INFRA_NR_CLK 37 macro
172 #define CK_INFRA_UART0_SEL (0 + CLK_INFRA_NR_CLK)
173 #define CK_INFRA_UART1_SEL (1 + CLK_INFRA_NR_CLK)
174 #define CK_INFRA_UART2_SEL (2 + CLK_INFRA_NR_CLK)
175 #define CK_INFRA_SPI0_SEL (3 + CLK_INFRA_NR_CLK)
176 #define CK_INFRA_SPI1_SEL (4 + CLK_INFRA_NR_CLK)
177 #define CK_INFRA_SPI2_SEL (5 + CLK_INFRA_NR_CLK)
178 #define CK_INFRA_PWM1_SEL (6 + CLK_INFRA_NR_CLK)
179 #define CK_INFRA_PWM2_SEL (7 + CLK_INFRA_NR_CLK)
180 #define CK_INFRA_PWM_BSEL (8 + CLK_INFRA_NR_CLK)
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H A Dmt7629-clk.h131 #define CLK_INFRA_NR_CLK 6 macro
/u-boot/dts/upstream/include/dt-bindings/clock/
H A Dmt8135-clk.h135 #define CLK_INFRA_NR_CLK 14 macro

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