Searched refs:CLK_GENERAL (Results 1 - 10 of 10) sorted by relevance

/u-boot/drivers/clk/rockchip/
H A Dclk_rv1108.c58 case CLK_GENERAL:
155 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
180 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
311 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
323 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
339 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
351 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
363 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
375 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
391 ulong parent_rate = rkclk_pll_get_rate(cru, CLK_GENERAL);
[all...]
H A Dclk_rk322x.c98 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
359 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
382 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
H A Dclk_rk3036.c96 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
300 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
H A Dclk_rk3128.c157 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
513 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
H A Dclk_rk3066.c423 rk3066_clk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
500 gclk_rate = rk3066_clk_pll_get_rate(priv->cru, CLK_GENERAL);
H A Dclk_rk3188.c389 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj);
467 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
H A Dclk_rk3288.c440 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
754 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
798 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
H A Dclk_rk3328.c235 case CLK_GENERAL:
296 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
/u-boot/arch/arm/mach-rockchip/rk3288/
H A Drk3288.c160 { "gpll", CLK_GENERAL },
/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dclock.h41 CLK_GENERAL, enumerator in enum:rk_clk_id

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