Searched refs:CFG_SYS_DCSRBAR (Results 1 - 22 of 22) sorted by relevance
| /u-boot/arch/arm/include/asm/arch-ls102xa/ |
| H A D | config.h | 14 #define CFG_SYS_DCSRBAR 0x20000000 macro
16 #define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00220000)
17 #define SYS_FSL_DCSR_RCPM_ADDR (CFG_SYS_DCSRBAR + 0x00222000)
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| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | cpu_init.c | 317 u32 __iomem *plldgdcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
318 u32 __iomem *plldadcr1 = (void *)(CFG_SYS_DCSRBAR + 0x21c28);
319 u32 __iomem *dpdovrcr4 = (void *)(CFG_SYS_DCSRBAR + 0x21e80);
321 u32 __iomem *plldgdcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c40);
322 u32 __iomem *plldadcr2 = (void *)(CFG_SYS_DCSRBAR + 0x21c48);
324 u32 __iomem *plldgdcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c60);
325 u32 __iomem *plldadcr3 = (void *)(CFG_SYS_DCSRBAR + 0x21c68);
765 __be32 *p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb004c;
771 p = (void __iomem *)CFG_SYS_DCSRBAR + 0xb0108;
801 p = (void *)CFG_SYS_DCSRBAR
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| H A D | cmd_errata.c | 26 void __iomem *dcsr = (void *)CFG_SYS_DCSRBAR + 0xb0000;
123 u32 __iomem *plldgdcr = (void *)(CFG_SYS_DCSRBAR + 0x21c20);
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| H A D | fsl_corenet_serdes.c | 269 #define CFG_SYS_DCSRBAR 0x80000000 macro
327 u32 *p = (void *)CFG_SYS_DCSRBAR + 0x20114;
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| /u-boot/board/freescale/t104xrdb/ |
| H A D | spl.c | 49 out_be32((unsigned int *)(CFG_SYS_DCSRBAR + 0x20000),
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| H A D | tlb.c | 100 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/board/freescale/common/p_corenet/ |
| H A D | tlb.c | 134 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/board/freescale/t102xrdb/ |
| H A D | tlb.c | 87 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/board/keymile/kmcent2/ |
| H A D | tlb.c | 74 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/board/freescale/t208xqds/ |
| H A D | tlb.c | 115 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/board/freescale/t208xrdb/ |
| H A D | tlb.c | 115 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/board/freescale/t4rdb/ |
| H A D | tlb.c | 97 SET_TLB_ENTRY(1, CFG_SYS_DCSRBAR, CFG_SYS_DCSRBAR_PHYS,
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| /u-boot/arch/arm/cpu/armv7/ls102xa/ |
| H A D | ls102xa_psci.c | 45 void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
121 void *dcsr_epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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| H A D | cpu.c | 307 void *epu_base = (void *)(CFG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
309 (void *)(CFG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
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| /u-boot/include/configs/ |
| H A D | P2041RDB.h | 56 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| H A D | kmcent2.h | 146 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| H A D | T208xRDB.h | 68 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| H A D | T102xRDB.h | 105 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| H A D | T104xRDB.h | 74 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| H A D | T4240RDB.h | 49 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| H A D | T208xQDS.h | 68 #define CFG_SYS_DCSRBAR 0xf0000000 macro
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| /u-boot/arch/arm/include/asm/arch-fsl-layerscape/ |
| H A D | immap_lsch2.h | 14 #define CFG_SYS_DCSRBAR 0x20000000 macro
15 #define CFG_SYS_DCSR_DCFG_ADDR (CFG_SYS_DCSRBAR + 0x00140000)
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