Searched refs:L1_CACHE_LINE_SIZE (Results 1 - 12 of 12) sorted by relevance

/seL4-test-master/kernel/include/arch/x86/arch/64/mode/model/
H A Dsmp.h30 compile_assert(nodeInfoIsCacheSized, (sizeof(nodeInfo_t) % L1_CACHE_LINE_SIZE) == 0)
32 extern nodeInfo_t node_info[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE);
39 extern char nodeSkimScratch[CONFIG_MAX_NUM_NODES][sizeof(nodeInfo_t)] ALIGN(L1_CACHE_LINE_SIZE) VISIBLE SKIM_BSS;
/seL4-test-master/kernel/src/arch/x86/64/model/
H A Dsmp.c12 nodeInfo_t node_info[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE) VISIBLE;
13 char nodeSkimScratch[CONFIG_MAX_NUM_NODES][sizeof(nodeInfo_t)] ALIGN(L1_CACHE_LINE_SIZE);
/seL4-test-master/kernel/src/smp/
H A Dlock.c12 clh_lock_t big_kernel_lock ALIGN(L1_CACHE_LINE_SIZE);
/seL4-test-master/kernel/include/arch/arm/arch/machine/
H A Dhardware.h31 #define L1_CACHE_LINE_SIZE BIT(L1_CACHE_LINE_SIZE_BITS) macro
/seL4-test-master/kernel/include/arch/x86/arch/model/
H A Dstatedata.h65 compile_assert(x86_arch_global_state_padded, (sizeof(x86_arch_global_state_t) % L1_CACHE_LINE_SIZE) == 0)
67 extern x86_arch_global_state_t x86KSGlobalState[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE) SKIM_BSS;
/seL4-test-master/kernel/src/arch/x86/model/
H A Dstatedata.c23 x86_arch_global_state_t x86KSGlobalState[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE) SKIM_BSS;
/seL4-test-master/kernel/include/arch/x86/arch/machine/
H A Dhardware.h18 #define L1_CACHE_LINE_SIZE CONFIG_CACHE_LN_SZ macro
/seL4-test-master/kernel/include/arch/riscv/arch/machine/
H A Dhardware.h38 #define L1_CACHE_LINE_SIZE BIT(L1_CACHE_LINE_SIZE_BITS) macro
/seL4-test-master/kernel/src/arch/arm/
H A Dc_traps.c141 ALIGN(L1_CACHE_LINE_SIZE)
156 ALIGN(L1_CACHE_LINE_SIZE)
/seL4-test-master/kernel/include/
H A Dutil.h174 #define PAD_TO_NEXT_CACHE_LN(used) char padding[L1_CACHE_LINE_SIZE - ((used) % L1_CACHE_LINE_SIZE)]
/seL4-test-master/kernel/src/model/
H A Dstatedata.c18 SMP_STATE_DEFINE(smpStatedata_t, ksSMP[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE));
/seL4-test-master/kernel/src/arch/x86/kernel/
H A Dvspace.c486 if (cacheLineSize != L1_CACHE_LINE_SIZE) {
488 L1_CACHE_LINE_SIZE, cacheLineSize);

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