1/*
2 * Copyright 2014, General Dynamics C4 Systems
3 *
4 * SPDX-License-Identifier: GPL-2.0-only
5 */
6
7#pragma once
8
9#include <config.h>
10#include <types.h>
11#include <util.h>
12#include <object/structures.h>
13#include <arch/types.h>
14#include <plat/machine/devices.h>
15#include <arch/object/vcpu.h>
16#include <arch/object/iospace.h>
17#include <arch/object/ioport.h>
18#include <plat/machine.h>
19
20#include <mode/model/statedata.h>
21
22
23#define TSS_IO_MAP_SIZE (65536 / 8 / sizeof(word_t) + 1)
24
25typedef struct {
26    tss_t   tss;
27    word_t  io_map[TSS_IO_MAP_SIZE];
28} PACKED tss_io_t;
29
30NODE_STATE_BEGIN(archNodeState)
31/* Interrupt currently being handled, not preserved across kernel entries */
32NODE_STATE_DECLARE(interrupt_t, x86KScurInterrupt);
33/* Interrupt that the hardware believes we are currently handling (is marked in service
34 * in the APIC) but we have not yet gotten around to handling */
35NODE_STATE_DECLARE(interrupt_t, x86KSPendingInterrupt);
36/* Bitmask of all cores should receive the reschedule IPI */
37NODE_STATE_DECLARE(word_t, ipiReschedulePending);
38
39#ifdef CONFIG_VTX
40NODE_STATE_DECLARE(vcpu_t *, x86KSCurrentVCPU);
41#endif
42
43NODE_STATE_DECLARE(word_t, x86KSCurrentFSBase);
44NODE_STATE_DECLARE(word_t, x86KSCurrentGSBase);
45
46/* If a GP exception occurs and this is non NULL then the exception should return to
47 * this location instead of faulting. In addition the GP exception will clear this
48 * back to NULL */
49NODE_STATE_DECLARE(word_t, x86KSGPExceptReturnTo);
50
51NODE_STATE_TYPE_DECLARE(modeNodeState, mode);
52NODE_STATE_END(archNodeState);
53
54/* this is per core state grouped into a separate struct as it needs to be available
55 * at all times by the hardware, even when we are running in user mode */
56typedef struct x86_arch_global_state {
57    /* Task State Segment (TSS), contains currently running TCB in ESP0 */
58    tss_io_t x86KStss;
59    /* Global Descriptor Table (GDT) */
60    gdt_entry_t x86KSgdt[GDT_ENTRIES];
61    /* Interrupt Descriptor Table (IDT) */
62    idt_entry_t x86KSidt[IDT_ENTRIES];
63    PAD_TO_NEXT_CACHE_LN(sizeof(tss_io_t) + GDT_ENTRIES *sizeof(gdt_entry_t) + IDT_ENTRIES *sizeof(idt_entry_t));
64} x86_arch_global_state_t;
65compile_assert(x86_arch_global_state_padded, (sizeof(x86_arch_global_state_t) % L1_CACHE_LINE_SIZE) == 0)
66
67extern x86_arch_global_state_t x86KSGlobalState[CONFIG_MAX_NUM_NODES] ALIGN(L1_CACHE_LINE_SIZE) SKIM_BSS;
68
69extern asid_pool_t *x86KSASIDTable[];
70extern uint32_t x86KScacheLineSizeBits;
71extern user_fpu_state_t x86KSnullFpuState ALIGN(MIN_FPU_ALIGNMENT);
72
73#ifdef CONFIG_IOMMU
74extern uint32_t x86KSnumDrhu;
75extern vtd_rte_t *x86KSvtdRootTable;
76extern uint32_t x86KSnumIOPTLevels;
77extern uint32_t x86KSnumIODomainIDBits;
78extern uint32_t x86KSFirstValidIODomain;
79#endif
80
81#ifdef CONFIG_PRINTING
82extern uint16_t x86KSconsolePort;
83#endif
84#ifdef CONFIG_DEBUG_BUILD
85extern uint16_t x86KSdebugPort;
86#endif
87
88extern x86_irq_state_t x86KSIRQState[];
89
90extern word_t x86KSAllocatedIOPorts[NUM_IO_PORTS / CONFIG_WORD_SIZE];
91#ifdef CONFIG_KERNEL_MCS
92extern uint32_t x86KStscMhz;
93extern uint32_t x86KSapicRatio;
94#endif
95
96