Searched refs:ctrl (Results 1 - 25 of 36) sorted by relevance

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/seL4-refos-master/libs/libplatsupport/arch_include/arm/platsupport/arch/
H A Dgeneric_timer.h64 uintptr_t ctrl; local
65 COPROC_READ_WORD(CNTP_CTL, ctrl);
66 return ctrl;
69 static inline void generic_timer_write_ctrl(uintptr_t ctrl) argument
71 COPROC_WRITE_WORD(CNTP_CTL, ctrl);
76 uintptr_t ctrl = generic_timer_read_ctrl(); local
77 generic_timer_write_ctrl(ctrl | bits);
82 uintptr_t ctrl = generic_timer_read_ctrl(); local
83 generic_timer_write_ctrl(ctrl & bits);
/seL4-refos-master/projects/util_libs/libplatsupport/arch_include/arm/platsupport/arch/
H A Dgeneric_timer.h64 uintptr_t ctrl; local
65 COPROC_READ_WORD(CNTP_CTL, ctrl);
66 return ctrl;
69 static inline void generic_timer_write_ctrl(uintptr_t ctrl) argument
71 COPROC_WRITE_WORD(CNTP_CTL, ctrl);
76 uintptr_t ctrl = generic_timer_read_ctrl(); local
77 generic_timer_write_ctrl(ctrl | bits);
82 uintptr_t ctrl = generic_timer_read_ctrl(); local
83 generic_timer_write_ctrl(ctrl & bits);
/seL4-refos-master/kernel/src/drivers/timer/
H A Dpriv_timer.c28 priv_timer->ctrl = 0;
33 priv_timer->ctrl |= ((PRESCALE) << (TMR_CTRL_PRESCALE))
37 priv_timer->ctrl |= TMR_CTRL_ENABLE;
/seL4-refos-master/kernel/include/drivers/timer/
H A Darm_priv.h15 uint32_t ctrl; member in struct:timer
/seL4-refos-master/libs/libplatsupport/src/plat/bcm2837/
H A Dsystem_timer.c74 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
80 if (time >= ns && !(timer->regs->ctrl & BIT(SYSTEM_TIMER_MATCH))) {
81 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
94 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
105 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
H A Dspt.c107 spt->regs->ctrl = BIT(FREE_RUN_ENABLE) | BIT(COUNTER_WIDTH_BIT);
117 spt->regs->ctrl = 0;
157 spt->regs->ctrl = BIT(COUNTER_WIDTH_BIT) | (prescale_bits << PRESCALE_BIT) |
170 spt->regs->ctrl &= ~(BIT(TIMER_ENABLE));
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/bcm2837/
H A Dsystem_timer.c74 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
80 if (time >= ns && !(timer->regs->ctrl & BIT(SYSTEM_TIMER_MATCH))) {
81 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
94 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
105 timer->regs->ctrl = BIT(SYSTEM_TIMER_MATCH);
H A Dspt.c107 spt->regs->ctrl = BIT(FREE_RUN_ENABLE) | BIT(COUNTER_WIDTH_BIT);
117 spt->regs->ctrl = 0;
157 spt->regs->ctrl = BIT(COUNTER_WIDTH_BIT) | (prescale_bits << PRESCALE_BIT) |
170 spt->regs->ctrl &= ~(BIT(TIMER_ENABLE));
/seL4-refos-master/libs/libplatsupport/src/arch/arm/
H A Ddma330.c170 } ctrl; member in struct:dma330_map
237 return regs->ctrl.fsm & BIT(0);
239 return regs->ctrl.fsc & BIT(channel);
248 return regs->ctrl.dsr;
259 return regs->ctrl.ftm;
261 return regs->ctrl.ftc[channel];
274 v = regs->ctrl.dsr;
327 printf(" MGR PC: 0x%08x\n", regs->ctrl.dpc);
328 printf(" fs: 0x%08x\n", regs->ctrl.fsm);
329 printf(" Fault: 0x%08x\n", regs->ctrl
[all...]
/seL4-refos-master/projects/util_libs/libplatsupport/src/arch/arm/
H A Ddma330.c170 } ctrl; member in struct:dma330_map
237 return regs->ctrl.fsm & BIT(0);
239 return regs->ctrl.fsc & BIT(channel);
248 return regs->ctrl.dsr;
259 return regs->ctrl.ftm;
261 return regs->ctrl.ftc[channel];
274 v = regs->ctrl.dsr;
327 printf(" MGR PC: 0x%08x\n", regs->ctrl.dpc);
328 printf(" fs: 0x%08x\n", regs->ctrl.fsm);
329 printf(" Fault: 0x%08x\n", regs->ctrl
[all...]
/seL4-refos-master/libs/libplatsupport/src/plat/zynq7000/
H A Ddevcfg.h29 uint32_t ctrl; // 0x0000 Control member in struct:devcfg_regs
H A Dclock.c315 set_divs(volatile uint32_t* ctrl, uint8_t div0, uint8_t div1) argument
318 old_div0 = CLK_GET_DIVISOR(0, *ctrl);
320 CLK_SET_DIVISOR(0, *ctrl, div0);
321 CLK_SET_DIVISOR(1, *ctrl, div1);
323 CLK_SET_DIVISOR(1, *ctrl, div1);
324 CLK_SET_DIVISOR(0, *ctrl, div0);
330 set_div(volatile uint32_t* ctrl, uint8_t div0) argument
332 CLK_SET_DIVISOR(0, *ctrl, div0);
425 _decode_pll(clk_t* clk, volatile uint32_t** ctrl, volatile uint32_t** cfg) argument
429 *ctrl
[all...]
/seL4-refos-master/libs/libplatsupport/plat_include/bcm2837/platsupport/plat/
H A Dspt.h27 uint32_t ctrl; /* Control register for timer */ member in struct:arm_timer
H A Dsystem_timer.h50 uint32_t ctrl; member in struct:__anon512
/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/bcm2837/platsupport/plat/
H A Dspt.h27 uint32_t ctrl; /* Control register for timer */ member in struct:arm_timer
H A Dsystem_timer.h50 uint32_t ctrl; member in struct:__anon943
/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/zynq7000/
H A Ddevcfg.h29 uint32_t ctrl; // 0x0000 Control member in struct:devcfg_regs
H A Dclock.c315 set_divs(volatile uint32_t* ctrl, uint8_t div0, uint8_t div1) argument
318 old_div0 = CLK_GET_DIVISOR(0, *ctrl);
320 CLK_SET_DIVISOR(0, *ctrl, div0);
321 CLK_SET_DIVISOR(1, *ctrl, div1);
323 CLK_SET_DIVISOR(1, *ctrl, div1);
324 CLK_SET_DIVISOR(0, *ctrl, div0);
330 set_div(volatile uint32_t* ctrl, uint8_t div0) argument
332 CLK_SET_DIVISOR(0, *ctrl, div0);
425 _decode_pll(clk_t* clk, volatile uint32_t** ctrl, volatile uint32_t** cfg) argument
429 *ctrl
[all...]
/seL4-refos-master/libs/libvterm/src/
H A Dvterm.c138 void vterm_push_output_sprintf_ctrl(VTerm *vt, unsigned char ctrl, const char *fmt, ...) argument
140 if(ctrl >= 0x80 && !vt->mode.ctrl8bit)
141 vterm_push_output_sprintf(vt, "\e%c", ctrl - 0x40);
143 vterm_push_output_sprintf(vt, "%c", ctrl);
150 if(ctrl == C1_DCS)
/seL4-refos-master/projects/refos/impl/libs/libvterm/src/
H A Dvterm.c138 void vterm_push_output_sprintf_ctrl(VTerm *vt, unsigned char ctrl, const char *fmt, ...) argument
140 if(ctrl >= 0x80 && !vt->mode.ctrl8bit)
141 vterm_push_output_sprintf(vt, "\e%c", ctrl - 0x40);
143 vterm_push_output_sprintf(vt, "%c", ctrl);
150 if(ctrl == C1_DCS)
/seL4-refos-master/seL4_tools/elfloader-tool/src/plat/imx6/
H A Dplatform_init.c154 uint32_t ctrl; member in struct:gicc_map
186 gicc->ctrl = 0;
/seL4-refos-master/tools/elfloader/src/plat/imx6/
H A Dplatform_init.c154 uint32_t ctrl; member in struct:gicc_map
186 gicc->ctrl = 0;
/seL4-refos-master/seL4_tools/elfloader-tool/src/plat/tk1/
H A Dplatform_init.c230 uint32_t ctrl; member in struct:gicc_map
262 gicc->ctrl = 0;
/seL4-refos-master/tools/elfloader/src/plat/tk1/
H A Dplatform_init.c230 uint32_t ctrl; member in struct:gicc_map
262 gicc->ctrl = 0;
/seL4-refos-master/libs/libplatsupport/src/plat/imx6/
H A Dclock.c179 uint32_t ctrl; member in struct:pll2_regs
335 assert((regs->ctrl & PLL2_CTRL_LOCK) != 0);
336 assert((regs->ctrl & PLL2_CTRL_BYPASS) == 0);
337 assert((regs->ctrl & PLL2_CTRL_PWR_DOWN) == 0);
341 if (regs->ctrl & PLL2_CTRL_DIVSEL) {

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