/seL4-refos-master/libs/libplatsupport/arch_include/arm/platsupport/ |
H A D | clock.h | 20 struct clock_sys; 23 typedef struct clock_sys clock_sys_t; 37 struct clock_sys { struct 38 clk_t *(*get_clock)(clock_sys_t *clock_sys, enum clk_id id); 39 int (*gate_enable)(clock_sys_t *clock_sys, enum clock_gate gate, enum clock_gate_mode mode); 72 * @param[in] clock_sys A handle to the clock subsystem 75 static inline int clock_sys_valid(const clock_sys_t *clock_sys) argument 77 return clock_sys && clock_sys->priv; 84 * @param[out] clock_sys O 119 clk_get_clock(clock_sys_t *clock_sys, enum clk_id id) argument 142 clk_gate_enable(clock_sys_t *clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument [all...] |
/seL4-refos-master/projects/util_libs/libplatsupport/arch_include/arm/platsupport/ |
H A D | clock.h | 20 struct clock_sys; 23 typedef struct clock_sys clock_sys_t; 37 struct clock_sys { struct 38 clk_t *(*get_clock)(clock_sys_t *clock_sys, enum clk_id id); 39 int (*gate_enable)(clock_sys_t *clock_sys, enum clock_gate gate, enum clock_gate_mode mode); 72 * @param[in] clock_sys A handle to the clock subsystem 75 static inline int clock_sys_valid(const clock_sys_t *clock_sys) argument 77 return clock_sys && clock_sys->priv; 84 * @param[out] clock_sys O 119 clk_get_clock(clock_sys_t *clock_sys, enum clk_id id) argument 142 clk_gate_enable(clock_sys_t *clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument [all...] |
/seL4-refos-master/libs/libplatsupport/src/plat/imx31/ |
H A D | clock.c | 23 imx31_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument 29 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 31 clock_sys->priv = (void*)&clk_regs; 32 clock_sys->get_clock = &ps_get_clock; 33 clock_sys->gate_enable = &imx31_gate_enable;
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/seL4-refos-master/libs/libplatsupport/src/plat/omap3/ |
H A D | clock.c | 25 omap3_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument 31 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 33 clock_sys->priv = (void*)&clk_regs; 34 clock_sys->get_clock = &ps_get_clock; 35 clock_sys->gate_enable = &omap3_gate_enable;
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/imx31/ |
H A D | clock.c | 23 imx31_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument 29 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 31 clock_sys->priv = (void*)&clk_regs; 32 clock_sys->get_clock = &ps_get_clock; 33 clock_sys->gate_enable = &imx31_gate_enable;
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/omap3/ |
H A D | clock.c | 25 omap3_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument 31 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 33 clock_sys->priv = (void*)&clk_regs; 34 clock_sys->get_clock = &ps_get_clock; 35 clock_sys->gate_enable = &omap3_gate_enable;
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/seL4-refos-master/libs/libplatsupport/src/plat/bcm2837/ |
H A D | clock.c | 24 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 26 clock_sys->priv = (void*)0xdeadbeef; 27 clock_sys->get_clock = &ps_get_clock; 28 clock_sys->gate_enable = NULL;
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/bcm2837/ |
H A D | clock.c | 24 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 26 clock_sys->priv = (void*)0xdeadbeef; 27 clock_sys->get_clock = &ps_get_clock; 28 clock_sys->gate_enable = NULL;
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/seL4-refos-master/libs/libplatsupport/plat_include/tk1/platsupport/plat/ |
H A D | spi.h | 20 mux_sys_t* mux_sys, clock_sys_t* clock_sys,
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/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/tk1/platsupport/plat/ |
H A D | spi.h | 20 mux_sys_t* mux_sys, clock_sys_t* clock_sys,
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/seL4-refos-master/libs/libplatsupport/src/arch/arm/ |
H A D | clock.c | 61 static clk_t *get_clock_default(clock_sys_t *clock_sys UNUSED, enum clk_id id) 69 clk->clk_sys = clock_sys; 78 static int gate_enable_default(clock_sys_t *clock_sys UNUSED, enum clock_gate gate UNUSED, 85 int clock_sys_init_default(clock_sys_t *clock_sys) argument 87 clock_sys->get_clock = &get_clock_default; 88 clock_sys->gate_enable = &gate_enable_default; 90 clock_sys->priv = (void *)0xdeadbeef;
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/seL4-refos-master/projects/util_libs/libplatsupport/src/arch/arm/ |
H A D | clock.c | 61 static clk_t *get_clock_default(clock_sys_t *clock_sys UNUSED, enum clk_id id) 69 clk->clk_sys = clock_sys; 78 static int gate_enable_default(clock_sys_t *clock_sys UNUSED, enum clock_gate gate UNUSED, 85 int clock_sys_init_default(clock_sys_t *clock_sys) argument 87 clock_sys->get_clock = &get_clock_default; 88 clock_sys->gate_enable = &gate_enable_default; 90 clock_sys->priv = (void *)0xdeadbeef;
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/seL4-refos-master/libs/libplatsupport/plat_include/exynos4/platsupport/plat/ |
H A D | spi.h | 45 mux_sys_t* mux_sys, clock_sys_t* clock_sys,
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/seL4-refos-master/libs/libplatsupport/plat_include/exynos5/platsupport/plat/ |
H A D | spi.h | 50 mux_sys_t* mux_sys, clock_sys_t* clock_sys,
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H A D | clock.h | 84 clock_sys_t* clock_sys);
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/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/exynos4/platsupport/plat/ |
H A D | spi.h | 45 mux_sys_t* mux_sys, clock_sys_t* clock_sys,
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/seL4-refos-master/projects/util_libs/libplatsupport/plat_include/exynos5/platsupport/plat/ |
H A D | spi.h | 50 mux_sys_t* mux_sys, clock_sys_t* clock_sys,
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H A D | clock.h | 84 clock_sys_t* clock_sys);
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/seL4-refos-master/libs/libplatsupport/src/plat/exynos5/ |
H A D | clock.c | 290 exynos5_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument 296 clock_sys_common_init(clock_sys_t* clock_sys) argument 298 clock_sys->priv = (void*)&_clk_regs; 299 clock_sys->get_clock = &ps_get_clock; 300 clock_sys->gate_enable = &exynos5_gate_enable; 307 clock_sys_t* clock_sys) 339 return clock_sys_common_init(clock_sys); 343 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 354 return clock_sys_common_init(clock_sys); 305 exynos5_clock_sys_init(void* cpu, void* core, void* acp, void* isp, void* top, void* lex, void* r0x, void* r1x, void* cdrex, void* mem, clock_sys_t* clock_sys) argument
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos5/ |
H A D | clock.c | 290 exynos5_gate_enable(clock_sys_t* clock_sys, enum clock_gate gate, enum clock_gate_mode mode) argument 296 clock_sys_common_init(clock_sys_t* clock_sys) argument 298 clock_sys->priv = (void*)&_clk_regs; 299 clock_sys->get_clock = &ps_get_clock; 300 clock_sys->gate_enable = &exynos5_gate_enable; 307 clock_sys_t* clock_sys) 339 return clock_sys_common_init(clock_sys); 343 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 354 return clock_sys_common_init(clock_sys); 305 exynos5_clock_sys_init(void* cpu, void* core, void* acp, void* isp, void* top, void* lex, void* r0x, void* r1x, void* cdrex, void* mem, clock_sys_t* clock_sys) argument
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/seL4-refos-master/projects/util_libs/libethdrivers/src/plat/tx2/uboot/ |
H A D | dwc_eth_qos.c | 221 assert(clock_sys_valid(eqos->clock_sys)); 223 eqos->clk_slave_bus = clk_get_clock(eqos->clock_sys, CLK_AXI_CBB); 228 ret = clk_gate_enable(eqos->clock_sys, CLK_GATE_AXI_CBB, CLKGATE_ON); 234 ret = clk_gate_enable(eqos->clock_sys, CLK_GATE_EQOS_AXI, CLKGATE_ON); 240 eqos->clk_rx = clk_get_clock(eqos->clock_sys, CLK_EQOS_RX_INPUT); 245 ret = clk_gate_enable(eqos->clock_sys, CLK_GATE_EQOS_RX, CLKGATE_ON); 251 eqos->clk_ptp_ref = clk_get_clock(eqos->clock_sys, CLK_EQOS_PTP_REF); 256 ret = clk_gate_enable(eqos->clock_sys, CLK_GATE_EQOS_PTP_REF, CLKGATE_ON); 262 eqos->clk_tx = clk_get_clock(eqos->clock_sys, CLK_EQOS_TX); 267 ret = clk_gate_enable(eqos->clock_sys, CLK_GATE_EQOS_T [all...] |
/seL4-refos-master/libs/libplatsupport/src/mach/exynos/ |
H A D | spi.c | 253 spi_init_common(spi_bus_t* spi_bus, mux_sys_t* mux_sys, clock_sys_t* clock_sys) argument 261 if (clock_sys && clock_sys_valid(clock_sys)) { 262 spi_bus->clk = clk_get_clock(clock_sys, spi_bus->clkid); 402 mux_sys_t* mux_sys, clock_sys_t* clock_sys, 409 return spi_init_common(spi_bus, mux_sys, clock_sys); 444 return spi_init_common(spi_bus, &io_ops->mux_sys, &io_ops->clock_sys); 401 exynos_spi_init(enum spi_id id, void* base, mux_sys_t* mux_sys, clock_sys_t* clock_sys, spi_bus_t** ret_spi_bus) argument
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/seL4-refos-master/projects/util_libs/libplatsupport/src/mach/exynos/ |
H A D | spi.c | 253 spi_init_common(spi_bus_t* spi_bus, mux_sys_t* mux_sys, clock_sys_t* clock_sys) argument 261 if (clock_sys && clock_sys_valid(clock_sys)) { 262 spi_bus->clk = clk_get_clock(clock_sys, spi_bus->clkid); 402 mux_sys_t* mux_sys, clock_sys_t* clock_sys, 409 return spi_init_common(spi_bus, mux_sys, clock_sys); 444 return spi_init_common(spi_bus, &io_ops->mux_sys, &io_ops->clock_sys); 401 exynos_spi_init(enum spi_id id, void* base, mux_sys_t* mux_sys, clock_sys_t* clock_sys, spi_bus_t** ret_spi_bus) argument
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/seL4-refos-master/libs/libplatsupport/src/plat/exynos4/ |
H A D | clock.c | 322 clock_sys_common_init(clock_sys_t* clock_sys) argument 324 clock_sys->priv = (void*)_clk_regs; 325 clock_sys->get_clock = &ps_get_clock; 326 clock_sys->gate_enable = &exynos4_gate_enable; 331 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 341 return clock_sys_common_init(clock_sys);
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/seL4-refos-master/projects/util_libs/libplatsupport/src/plat/exynos4/ |
H A D | clock.c | 322 clock_sys_common_init(clock_sys_t* clock_sys) argument 324 clock_sys->priv = (void*)_clk_regs; 325 clock_sys->get_clock = &ps_get_clock; 326 clock_sys->gate_enable = &exynos4_gate_enable; 331 clock_sys_init(ps_io_ops_t* o, clock_sys_t* clock_sys) argument 341 return clock_sys_common_init(clock_sys);
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