Searched refs:cpu (Results 1 - 25 of 33) sorted by relevance

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/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/smp/
H A Dipi_inline.h20 static inline void doRemoteStall(word_t cpu) argument
22 doRemoteOp0Arg(IpiRemoteCall_Stall, cpu);
25 static inline void doRemoteswitchFpuOwner(user_fpu_state_t *new_owner, word_t cpu) argument
27 doRemoteOp1Arg(IpiRemoteCall_switchFpuOwner, (word_t)new_owner, cpu);
52 doRemoteClearCurrentVCPU(word_t cpu) argument
54 doRemoteOp0Arg(IpiRemoteCall_ClearCurrentVCPU, cpu);
58 doRemoteVMCheckBoundNotification(word_t cpu, tcb_t *tcb) argument
60 doRemoteOp1Arg(IpiRemoteCall_VMCheckBoundNotification, cpu, (word_t)tcb);
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/kernel/
H A Dtlb_bitmap.h34 tlb_bitmap_set(vspace_root_t *root, word_t cpu) argument
36 assert(cpu < TLBBITMAP_ROOT_BITS && cpu <= wordBits);
37 root[TLBBITMAP_ROOT_MAKE_INDEX(cpu)].words[0] |= TLBBITMAP_ROOT_MAKE_BIT(cpu);
41 tlb_bitmap_unset(vspace_root_t *root, word_t cpu)
43 assert(cpu < TLBBITMAP_ROOT_BITS && cpu <= wordBits);
44 root[TLBBITMAP_ROOT_MAKE_INDEX(cpu)].words[0] &= ~TLBBITMAP_ROOT_MAKE_BIT(cpu);
[all...]
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/smp/
H A Dipi_inline.h20 static inline void doRemoteStall(word_t cpu) argument
22 doRemoteOp0Arg(IpiRemoteCall_Stall, cpu);
26 static inline void doRemoteswitchFpuOwner(user_fpu_state_t *new_owner, word_t cpu) argument
28 doRemoteOp1Arg(IpiRemoteCall_switchFpuOwner, (word_t)new_owner, cpu);
/seL4-l4v-10.1.1/seL4/include/smp/
H A Dlock.h63 clh_is_ipi_pending(word_t cpu) argument
65 return big_kernel_lock.node_owners[cpu].ipi == 1;
70 irqPath, word_t cpu, int memorder)
75 (void *) big_kernel_lock.node_owners[cpu].node, (void **) &prev,
77 if (clh_is_ipi_pending(cpu)) {
91 clh_lock_acquire(word_t cpu, bool_t irqPath) argument
94 big_kernel_lock.node_owners[cpu].node->value = CLHState_Pending;
96 prev = sel4_atomic_exchange(&big_kernel_lock.head, irqPath, cpu, __ATOMIC_ACQUIRE);
98 big_kernel_lock.node_owners[cpu].next = prev;
102 while (big_kernel_lock.node_owners[cpu]
69 sel4_atomic_exchange(void* ptr, bool_t irqPath, word_t cpu, int memorder) argument
122 clh_lock_release(word_t cpu) argument
[all...]
H A Dipi.h94 /* Run a synchronous function on a core specified by cpu.
99 * @param cpu core to run function on
101 static void inline doRemoteOp(IpiRemoteCall_t func, word_t data1, word_t data2, word_t data3, word_t cpu)
103 doRemoteMaskOp(func, data1, data2, data3, BIT(cpu));
116 * @param cpu[mask] cores to run function on
141 static void inline doRemoteOp0Arg(IpiRemoteCall_t func, word_t cpu)
143 doRemoteOp(func, 0, 0, 0, cpu);
147 doRemoteOp1Arg(IpiRemoteCall_t func, word_t data1, word_t cpu)
149 doRemoteOp(func, data1, 0, 0, cpu);
153 doRemoteOp2Arg(IpiRemoteCall_t func, word_t data1, word_t data2, word_t cpu)
[all...]
/seL4-l4v-10.1.1/isabelle/src/Pure/General/
H A Dtiming.scala40 sealed case class Timing(elapsed: Time, cpu: Time, gc: Time)
42 def is_zero: Boolean = elapsed.is_zero && cpu.is_zero && gc.is_zero
43 def is_relevant: Boolean = elapsed.is_relevant || cpu.is_relevant || gc.is_relevant
45 def resources: Time = cpu + gc
54 def + (t: Timing): Timing = Timing(elapsed + t.elapsed, cpu + t.cpu, gc + t.gc)
57 elapsed.message + " elapsed time, " + cpu.message + " cpu time, " + gc.message + " GC time"
67 elapsed.message_hms + " elapsed time, " + resources.message_hms + " cpu time" + factor_text
75 JSON.Object("elapsed" -> elapsed.seconds, "cpu"
[all...]
/seL4-l4v-10.1.1/l4v/isabelle/src/Pure/General/
H A Dtiming.scala40 sealed case class Timing(elapsed: Time, cpu: Time, gc: Time)
42 def is_zero: Boolean = elapsed.is_zero && cpu.is_zero && gc.is_zero
43 def is_relevant: Boolean = elapsed.is_relevant || cpu.is_relevant || gc.is_relevant
45 def resources: Time = cpu + gc
54 def + (t: Timing): Timing = Timing(elapsed + t.elapsed, cpu + t.cpu, gc + t.gc)
57 elapsed.message + " elapsed time, " + cpu.message + " cpu time, " + gc.message + " GC time"
67 elapsed.message_hms + " elapsed time, " + resources.message_hms + " cpu time" + factor_text
75 JSON.Object("elapsed" -> elapsed.seconds, "cpu"
[all...]
/seL4-l4v-10.1.1/l4v/misc/benchmark/
H A Dspeedstep.sh11 FREQ_AVAIL=/sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies
12 FREQ_CONTROL=/sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
13 FREQ_GOV=/sys/devices/system/cpu/cpu0/cpufreq/scaling_governor
14 FREQ_CUR=/sys/devices/system/cpu/cpu0/cpufreq/scaling_cur_freq
/seL4-l4v-10.1.1/seL4/src/machine/
H A Dfpu.c36 void switchFpuOwner(user_fpu_state_t *new_owner, word_t cpu) argument
39 if (cpu != getCurrentCPUIndex()) {
40 doRemoteswitchFpuOwner(new_owner, cpu);
/seL4-l4v-10.1.1/seL4/include/model/
H A Dsmp.h24 archNodeState_t cpu; member in struct:smpStatedata
H A Dstatedata.h34 #define MODE_NODE_STATE_ON_CORE(_state, _core) ksSMP[(_core)].cpu.mode._state
35 #define ARCH_NODE_STATE_ON_CORE(_state, _core) ksSMP[(_core)].cpu._state
/seL4-l4v-10.1.1/l4v/misc/regression/
H A Dcpuusage.py77 self.cpu = 0.0
123 if total + 1e-9 < self.cpu:
128 warnings.warn("cpu non-monotonic: %.15f -> %.15f, pid=%d, cmd=%s" %
129 (self.cpu, total, self.pid, cmd),
134 self.cpu = update()
147 self.cpu = update()
154 return self.cpu
187 cpu = 0
198 print('Total cpu %f seconds' % m.cpu_usage(), file=sys.stderr)
/seL4-l4v-10.1.1/HOL4/developers/
H A Dgit-regression-build.sh111 cpu=$(perl -e "$cpuperlprog" < /proc/cpuinfo)
114 cpu=$(system_profiler SPHardwareDataType |
147 echo "Cpu: $cpu" &&
/seL4-l4v-10.1.1/seL4/include/machine/
H A Dfpu.h31 /* Switch the current owner of the FPU state on the core specified by 'cpu'. */
32 void switchFpuOwner(user_fpu_state_t *new_owner, word_t cpu);
/seL4-l4v-10.1.1/HOL4/src/holyhammer/provers/
H A Deprover.sh13 timeout $1 ./eprover -s --cpu-limit=$1 --auto-schedule --tptp3-in \
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/
H A Dmachine.h268 static inline void x86_write_fs_base(word_t base, cpu_id_t cpu) argument
270 if (base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu)) {
271 ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu) = base;
276 static inline void x86_write_gs_base(word_t base, cpu_id_t cpu) argument
278 if (likely(base != ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu))) {
279 ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu) = base;
284 static inline word_t x86_read_fs_base(cpu_id_t cpu) argument
286 return ARCH_NODE_STATE_ON_CORE(x86KSCurrentFSBase, cpu);
289 static inline word_t x86_read_gs_base(cpu_id_t cpu) argument
291 return ARCH_NODE_STATE_ON_CORE(x86KSCurrentGSBase, cpu);
[all...]
/seL4-l4v-10.1.1/seL4/include/arch/x86/arch/64/mode/fastpath/
H A Dfastpath.h166 cpu_id_t cpu = getCurrentCPUIndex(); local
177 x86_write_fs_base(base, SMP_TERNARY(cpu, 0));
180 x86_write_gs_base(base, SMP_TERNARY(cpu, 0));
/seL4-l4v-10.1.1/seL4/src/arch/x86/64/
H A Dc_traps.c172 cpu_id_t cpu = getCurrentCPUIndex(); local
184 x86_write_fs_base(base, SMP_TERNARY(cpu, 0));
187 x86_write_gs_base(base, SMP_TERNARY(cpu, 0));
/seL4-l4v-10.1.1/seL4/include/arch/arm/arch/object/
H A Dvcpu.h99 void vcpu_restore(vcpu_t *cpu);
100 void vcpu_switch(vcpu_t *cpu);
/seL4-l4v-10.1.1/seL4/src/arch/arm/machine/
H A Dgic_pl390.c40 #error GIC_PL390_CONTROLLER_PPTR must be defined for virtual memory access to the gic cpu interface
96 * reset int target to current cpu
192 * 0b01 - send the ipi to all CPU interfaces except the cpu interface.
216 #error GIC_PL400_VCPUCTRL_PPTR must be defined for virtual memory access to the gic virtual cpu interface control
/seL4-l4v-10.1.1/isabelle/src/Pure/System/
H A Dbash.scala157 case List(Value.Long(elapsed), Value.Long(cpu)) =>
158 Timing(Time.ms(elapsed), Time.ms(cpu), Time.zero)
/seL4-l4v-10.1.1/l4v/isabelle/src/Pure/System/
H A Dbash.scala157 case List(Value.Long(elapsed), Value.Long(cpu)) =>
158 Timing(Time.ms(elapsed), Time.ms(cpu), Time.zero)
/seL4-l4v-10.1.1/isabelle/src/Pure/Admin/
H A Dbuild_status.scala133 entry.timing.cpu.ms,
136 entry.ml_timing.cpu.ms,
454 """ using 1:3 smooth sbezier title "cpu time (smooth)" """,
455 """ using 1:3 smooth csplines title "cpu time" """)
463 """ using 1:5 smooth sbezier title "ML cpu time (smooth)" """,
464 """ using 1:5 smooth csplines title "ML cpu time" """)
/seL4-l4v-10.1.1/l4v/isabelle/src/Pure/Admin/
H A Dbuild_status.scala133 entry.timing.cpu.ms,
136 entry.ml_timing.cpu.ms,
454 """ using 1:3 smooth sbezier title "cpu time (smooth)" """,
455 """ using 1:3 smooth csplines title "cpu time" """)
463 """ using 1:5 smooth sbezier title "ML cpu time (smooth)" """,
464 """ using 1:5 smooth csplines title "ML cpu time" """)
/seL4-l4v-10.1.1/isabelle/src/Pure/PIDE/
H A Dmarkup.scala353 val CPU = new Properties.Double("cpu")
359 Elapsed(timing.elapsed.seconds) ::: CPU(timing.cpu.seconds) ::: GC(timing.gc.seconds)
363 case (Elapsed(elapsed), CPU(cpu), GC(gc)) =>
364 Some(new isabelle.Timing(Time.seconds(elapsed), Time.seconds(cpu), Time.seconds(gc)))

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